In this paper, we present a fractionally injection-locked frequency multiplication technique that can solve the tradeoff between the selectable
frequency step and phase noise of injection-locked frequency multipliers (ILFMs). For a given output frequency step, the phase noise of the
proposed ILFM is lower than that of conventional ILFMs because higher-frequency signals can be injected. The proposed ILFM was fabricated
using a 180nm Si complementary metal oxide semiconductor (CMOS) process. 1/2-, 1/3-, 1/4-, and 1/6-integral frequency multiplications were
realized, which means that the output frequency resolution is 6 times as high as that of conventional ILFM. When the reference frequency was
100 MHz, the measured phase noise at 725 (¼ 100 29=4)MHz was 120 dBc/Hz at a 1MHz offset, and that at 767 (¼ 100 23=3)MHz was
119 dBc/Hz at 1 MHz offset.
各種検索
サポート
ヘルプ