Scaling limit for InGaAs/GaAsSb heterojunction double-gate tunnel FETs from the viewpoint of direct band-to-band tunneling from source to drain induced off-characteristics deterioration
<jats:title>Abstract</jats:title>
<jats:p>In this paper, we propose a method to classify the tunneling currents using simulations. The main objective is to investigate the effects of the direct source-to-drain tunneling, which is undesirable, in the case of devices with extremely short channels. We performed the classification of tunneling currents in InGaAs/GaAsSb heterojunction double-gate tunnel FETs based on this method, and we found that the direct-tunneling component increased dramatically in short-channel cases. The channel length must be 20 nm or longer, in case of InGaAs/GaAsSb heterojunction double-gate tunnel FETs, to limit the off-current within 10 pA/µm, which is required as per the ITRS LP.</jats:p>
各種検索
サポート
ヘルプ