計算工学講演会論文集 = Proceedings of the Conference on Computational Engineering and Science / 日本計算工学会 編
英文:
巻, 号, ページ
Vol. 25
pp. 6p
出版年月
2020年6月
出版者
和文:
東京 : 日本計算工学会
英文:
会議名称
和文:
英文:
開催地
和文:
英文:
アブストラクト
Field-programmable gate arrays (FPGAs) have garnered significant interest in research on highperformance computing because their computation and communication capabilities have drastically improved in recent years due to advances in semiconductor integration technologies that rely on Moore’s Law. In addition to improving FPGA performance, toolchains for the development of FPGAs in OpenCL have been developed and offered by FPGA vendors that reduce the programming effort required. These improvements reveal the possibility of implementing a concept to enable on-the-fly offloading computation at which CPUs/GPUs perform poorly to FPGAs while performing low-latency data movement. We think that this concept is k-ey to improving the performance of heterogeneous supercomputers using accelerators such as the GPU. In this paper, we propose a GPU-FPGA-accelerated simulation based on the concept and show our implementation with OpenCL-enabled GPU–FPGA DMA method. The results of experiments show that our proposed method can always achieve better performance than GPU-based implementation and we believe that realizing GPU–FPGA-accelerated simulation is the most significant difference between our work and previous studies.
各種検索
サポート
ヘルプ