FPGA accelerators can obtain higher computation performance and better power efficiency than CPUs and GPUs, because designers can implement circuits that realize application-specific pipelined hardware and data supply system. In this paper, we propose an approach of sorting acceleration by using a large FPGA. Sorting is an extremely important computation kernel that has been tried to be accelerated in lots of fields. We design and implement the proposed FPGA accelerator, and then evaluate its performance by comparing with a modern desktop computer. From this evaluation, we show how sorting is accelerated.
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