"Hiroyoshi Tanabe,Akira Jinguji,Atsushi Takahashi","Weakly guiding approximation of a three dimensional waveguide model for extreme ultraviolet lithography simulation",,"Journal of the Optical Society of America A","Optica Publishing Group","Vol. 41","Issue 8","pp. 1491-1499",2024,July
"Kazuya Taniguchi,Satoshi Tayu,Atsushi Takahashi,Mathieu Molongo,Makoto Minami,Katsuya Nishioka","Two-layer Bottleneck Channel Track Assignment for Analog VLSI",,"IPSJ Trans. on System LSI Design Methodology",,"Vol. 17",,"pp. 67-76",2024,June
"Zezhong Wang,Masayuki Shimoda,Atsushi Takahashi","BCA Channel Routing to Minimize Wirelength for Generalized Channel Problem",,"Proc. IEEE International Symposium on Circuits and Systems (ISCAS '24)",,,,,2024,May
"Hiroyoshi Tanabe,Akira Jinguji,Atsushi Takahashi","Pre-training CNN for fast EUV lithography simulation including M3D effects",,"Proc. SPIE 12954, DTCO and Computational Patterning III, 129540I","Society of Photo-Optical Instrumentation Engineers (SPIE)",,,,2024,Apr.
"Kazuya Taniguchi,Satoshi Tayu,Atsushi Takahashi,Mathieu Molongo,Makoto Minami,Katsuya Nishioka","A Fast Three-layer Bottleneck Channel Track Assignment with Layout Constraints using ILP",,"Proc. the 25th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2024)",,,,"pp. 50-55",2024,Mar.
"徐紫昂,田湯 智,高橋篤司,モロンゴ マチュー,南 誠,西岡克也","ダブルビア制約付きペア対称配線問題に対するSMTソルバを用いたテンプレート配線手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2023-102)",,"Vol. 123","No. 390","pp. 18-23",2024,Feb.
"Zezhong Wang,Masayuki Shimoda,Atsushi Takahashi","Single Trunk Routing Problem for Generalized Channel","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2023-104)",,"Vol. 123","No. 390","pp. 30-35",2024,Feb.
"谷口和弥,田湯 智,高橋篤司,モロンゴ マチュー,南 誠,西岡克也","端子上下配置3層ボトルネック配線に対するトラック割当て法の提案","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2023-103)",,"Vol. 123","No. 390","pp. 24-29",2024,Feb.
"Hiroyoshi Tanabe,Akira Jinguji,Atsushi Takahashi","Accelerating extreme ultraviolet lithography simulation with weakly guiding approximation and source position dependent transmission cross coefficient formula",,"Journal of Micro/Nanopatterning, Materials, and Metrology",,"Vol. 23","Issue 1","  014201",2024,Jan.
"Hiroyoshi Tanabe,Akira Jinguji,Atsushi Takahashi","Accelerating EUV lithography simulation with weakly guiding approximation and STCC formula",,"Proc. SPIE 12750, International Conference on Extreme Ultraviolet Lithography 2023, 127500D","Society of Photo-Optical Instrumentation Engineers (SPIE)",,,,2023,Nov.
"Yukihide Kohira,Haruki Nakayama,Naoki Nonaka,Tomomi Matsui,Atsushi Takahashi,Chikaaki Kodama","A formulation of mask optimization into QUBO model for Ising machines",,"Proc. SPIE 12751, Photomask Technology 2023, 127511D",,,,,2023,Nov.
"山本 克治,神宮司 明良,高橋 篤司","MEDAバイオチップのための液滴運搬経路探索アルゴリズム",,"DAシンポジウム2023 論文集",,,,"pp. 173-179",2023,Aug.
"徐 紫昂,田湯 智,高橋 篤司,モロンゴ マチュー,南 誠,西岡 克也","ダブルビア制約付きコモンセントロイド配置におけるペア対称配線手法",,"DAシンポジウム2023 論文集",,,,"pp. 207-212",2023,Aug.
"谷口和弥,田湯 智,高橋篤司,モロンゴ マチュー,南 誠,西岡克也","整数計画法を用いた3層ボトルネックチャネルトラック割当て法",,"DAシンポジウム2023 論文集",,,,"pp. 199-206",2023,Aug.
"Onjira Duongthipthewa,Koonlachat Meesublak,Atsushi Takahashi,Chowarit Mitsantisuk","Detection Welding Performance of Industrial Robot Using Machine Learning",,"Proc. International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC)",,,,,2023,Aug.
"Hiroyoshi Tanabe,Akira Jinguji,Atsushi Takahashi","Evaluation of convolutional neural network for fast extreme ultraviolet lithography simulation using imec 3 nm node mask patterns",,"Journal of Micro/Nanopatterning, Materials and Metrology (JM3)","Society of Photo-optical Instrumentation Engineers","Vol. 22","Issue 2","  024201",2023,June
"Hiroyoshi Tanabe,Akira Jinguji,Atsushi Takahashi","Evaluation of CNN for fast EUV lithography simulation using iN3 logic mask patterns",,"Proc. SPIE 12495, Advanced Lithography + Patterning 2023, 124951J",,,,,2023,Apr.
"Atsushi Takahashi","Report on the 28th Asia and South Pacific Design Automation Conference",,"IEEE Design & Test",,"vol. 40","issue 3","pp. 62-63",2023,Apr.
"齊藤颯太,堀本 遊,高橋篤司,小平行秀,児玉親亮","ボロノイ図を用いたSRAF配置とLUTベース光強度評価による高速SRAF最適化手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2022-80)",,"Vol. 122","No. 402","pp. 43-48",2023,Mar.
"堀本 遊,齊藤颯太,高橋篤司,小平行秀,児玉親亮","振幅成分を利用した補正による忠実度の高いマスクパターン生成手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2022-79)",,"Vol. 122","No. 402","pp. 37-42",2023,Mar.
"谷口和弥,田湯 智,高橋篤司,モロンゴ マチュー,南 誠,西岡克也","ボトルネック配線における配線可能性向上のための配線交差を考慮したトラック割当て法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2022-101)",,"Vol. 122","No. 402","pp. 149-154",2023,Mar.
"徐 紫昂,田湯 智,高橋篤司,モロンゴ マチュー,南 誠,西岡克也","共通信号制約付きコモンセントロイド配置におけるペア対称配線手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2022-102)",,"Vol. 122","No. 402","pp. 155-160",2023,Mar.
"Surachai Rodsai,Anusorn Iamrurksiri,Chowarit Mitsantisuk,Atsushi Takahashi","Point Cloud Based Guidance for Autonomous Mobile Robot in Sugarcane Plantation",,"Proc. International Symposium on Instrumentation, Control, Artificial Intelligence, and Robotics (ICA-SYMP)",,,,"pp. 15-18",2023,Feb.
"Atsushi Takahashi","Message from the Editor-in-Chief",,"IPSJ Transactions on System LSI Design Methodology",,"vol. 16",,,2023,Feb.
"Atsushi Takahashi","Proceedings of the 28th Asia and South Pacific Design Automation Conference, ASPDAC 2023","ASPDAC '23: 28th Asia and South Pacific Design Automation Conference",,,,,,2023,Jan.
"齊藤颯太,高橋篤司","LUTベースの光強度推定による高速なSRAF最適化手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2022-40)",,"Vol. 122","No. 283","pp. 121-126",2022,Nov.
"野中尚貴,小平行秀,高橋篤司,児玉親亮","ボロノイ分割と繰り返し改善によるマスク最適化手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2022-41)",,"Vol. 122","No. 283","pp. 127-132",2022,Nov.
"Hiroyoshi Tanabe,Atsushi Takahashi","Data augmentation in extreme ultraviolet lithography simulation using convolutional neural network",,"Journal of Micro/Nanopatterning, Materials and Metrology (JM3)",,"Vol. 21","Issue 4","  041602",2022,Oct.
"Kazuya Taniguchi,Satoshi Tayu,Atsushi Takahashi,Yukichi Todoroki,Makoto Minami","Bottleneck Channel Routing to Reduce the Area of Analog VLSI",,"Proc. the 24th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2022)",,,,"pp. 26-31",2022,Oct.
"徐紫昂,高橋篤司,轟祐吉,南誠","コモンセントロイド配置におけるペア対称配線の提案",,"DAシンポジウム2022 論文集",,,,"pp. 21-26",2022,Aug.
"Hiroyoshi Tanabe,Atsushi Takahashi","Data augmentation in EUV lithography simulation based on convolutional neural network","Proc. SPIE 12052, Advanced Lithography + Patterning 2022, 120520T",,,,,,2022,May
"谷口和弥,田湯智,高橋篤司,轟祐吉,南誠","アナログ集積回路面積削減のためのボトルネックチャネル配線の提案","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2021-77)",,"Vol. 121","No. 412","pp. 7-12",2022,Mar.
"高橋篤司","より大きな見返りを",,"電子情報通信学会誌",,"Vol. 105","No. 3",,2022,Mar.
"Atsushi Takahashi","Message from the Editor-in-Chief",,"IPSJ Transactions on System LSI Design Methodology",,"vol. 15",,,2022,Feb.
"小平行秀,中山晴貴,野中尚貴,松井知己,高橋篤司,児玉親亮","シミュレーテッド量子アニーリングを用いたマスク最適化手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2021-45)",,"Vol. 121","No. 277","pp. 162-167",2021,Dec.
"Hiroyoshi Tanabe,Shimpei Sato,Atsushi Takahashi","Fast EUV lithography simulation using convolutional neural network",,"Journal of Micro/Nanopatterning, Materials and Metrology (JM3)",,"Vol. 20","No. 4","pp. 1-14",2021,Sept.
"野中尚貴,小平行秀,東梨奈,松井知己,高橋篤司,児玉親亮","勾配判定法と劣勾配法を用いたマスク最適化","第34回 回路とシステムワークショップ","第34回 回路とシステムワークショップ 論文集",,,,"pp. 213-218",2021,Aug.
"Yuta Ukon,Shimpei Sato,Atsushi Takahashi","Design Method of Variable-Latency Circuit with Tunable Approximate Completion-Detection Mechanism",,"IEICE Transactions on Electronics",,"Vol. E104-C","No. 7","pp. 309-318",2021,July
"高橋篤司","基礎・境界ソサイエティ会長として思うこと",,"電子情報通信学会 基礎・境界ソサイエティ Fundamentals Review",,"Vol. 15","No. 1",,2021,July
"Tahsin Shameem,Shimpei Sato,Atsushi Takahashi,Hiroyoshi Tanabe,Yukihide Kohira,Chikaaki Kodama","A Fast LUT Based Point Intensity Computation for OPC Algorithm",,"Proc. the 23rd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2021)",,,,"pp. 92-97",2021,Mar.
"Hiroyoshi Tanabe,Shimpei Sato,Atsushi Takahashi","Fast 3D lithography simulation by convolutional neural network",,"Proc. SPIE 11614, Design-Process-Technology Co-optimization XV 2021, 116140M",,,,"pp. 1-8",2021,Feb.
"Atsushi Takahashi","Message from the Editor-in-Chief",,"IPSJ Transactions on System LSI Design Methodology",,"vol. 14",,,2021,Feb.
"Hiroyoshi Tanabe,Shimpei Sato,Atsushi Takahashi","Fast 3D lithography simulation by convolutional neural network: POC study",,"Proc. SPIE 11518, Photomask Technology 2020, 115180L",,,,,2020,Sept.
"Tahsin Binte Shameem,Atsushi Takahashi,Hiroyoshi Tanabe,Yukihide Kohira,Chikaaki Kodama","A Fast Look Up Table Based Lithography Simulator with SOCS Model for OPC Algorithm",,"Proc. DA Symposium 2020, IPSJ Symposium Series",,,,"pp. 142-149",2020,Sept.
"Shimpei Sato,Kano Akagi,Atsushi Takahashi","A Fast Length Matching Routing Pattern Generation Method for Set-Pair Routing Problem Using Selective Pin-Pair Connections",,"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",,"Vol. E103-A","No. 9","pp. 1037-1044",2020,Sept.
"高橋秀和,佐藤真平,高橋篤司","機械学習を用いたリソグラフィホットスポット検出手法と評価に関して","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2019-106)",,"Vol. 119","No. 443","pp. 71-76",2020,Mar.
"Rina Azuma,Yukihide Kohira,Tomomi Matsui,Atsushi Takahashi,Chikaaki Kodama","Process variation-aware mask optimization with iterative improvement by subgradient method and boundary ?ipping",,"Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 113280O",,,,"pp. 1-7",2020,Mar.
"Hidekazu Takahashi,Hiroki Ogura,Shimpei Sato,Atsushi Takahashi,Chikaaki Kodama","A feature selection method for weak classifier based hotspot detection",,"Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 113281E",,,,"pp. 1-7",2020,Mar.
"和田邦彦,佐藤真平,高橋篤司","集合対間配線における配線長差削減を考慮した端子対間配線手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2019-95)",,"Vol. 119","No. 443","pp. 7-12",2020,Mar.
"東梨奈,小平行秀,松井知己,高橋篤司,児玉親亮","ラグランジュ緩和法と境界Flippingによるプロセスばらつきを考慮したピクセルベースマスク最適化手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2019-105)",,"Vol. 119","No. 443","pp. 65-70",2020,Mar.
"Atsushi Takahashi","Message from the Editor-in-Chief",,"IPSJ Transactions on System LSI Design Methodology",,"vol. 13",,,2020,Feb.
"Pathawee Phonwiphat,Warut Pannakkong,Pisal Yenradee,Kittipong Ekkachai,Atsushi Takahashi","An Intelligent System for Identifying Feasible Routes for Truck Routing Problem: An Application to a Thai Adhesive and Sealant Company (ATASC)",,"Proc. International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON)",,,,"pp. 905-910",2020,Jan.
"Shimpei Sato,Eijiro Sassa,Yuta Ukon,Atsushi Takahashi","A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution",,"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",,"Vol. E102-A","No. 12","pp. 1760-1769",2019,Dec.
"小椋弘貴,高橋秀和,佐藤真平,高橋篤司","ホットスポットテストケースに用いられるデータベースの分析",,"電子情報通信学会技術研究報告",,"Vol. 119","No. 282","pp. 191-196",2019,Nov.
"小平行秀,東梨奈,松井知己,高橋篤司,児玉親亮","劣勾配法によるプロセスばらつきを考慮したマスク最適化手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2019-53)",,"Vol. 119","No. 282","pp. 197-202",2019,Nov.
"和田邦彦,大和田真由,山本克治,堀本遊,佐藤真平,高橋篤司","グラフの位相埋め込みの配置配線パズルへの適用に関する一検討",,"情報処理学会研究報告",,"Vol. 2019-SLDM-189","No. 31","pp. 1-6",2019,Nov.
"Hidekazu Takahashi,Shimpei Sato,Atsushi Takahashi","A Fast Hotspot Detector Based on Local Features Using Concentric Circle Area Sampling",,"Proc. the 22nd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2019)",,,,"pp. 316-321",2019,Oct.
"Atsushi Takahashi,Hidekazu Takahashi,Hiroki Ogura,Shimpei Sato","Hotspot Detection Methods and their Evaluation in Advanced Lithography",,"Proc. the 16th International SoC Design Conference (ISOCC '19)",,,,"p. 121",2019,Oct.
"高橋秀和,佐藤真平,高橋篤司","CCASを用いた局所特徴量に基づくリソグラフィホットスポット検出器の検討",,"DAシンポジウム2019 論文集",,,,"pp. 99-104",2019,Aug.
"Shimpei Sato,Eijiro Sassa,Yuta Ukon,Atsushi Takahashi","A Low Area Overhead Design for High-Performance General-Synchronous Circuits with Speculative Execution",,"Proc. IEEE International Symposium on Circuits and Systems (ISCAS '19)",,,,,2019,May
"Pruttapon Maolanon,Kanjanapan Sukvichai,Nattapon Chayopitak,Atsushi Takahashi","Indoor Room Identify and Mapping with Virtual based SLAM using Furnitures and Household Objects Relationship based on CNNs",,"Proc. International Conference of Information and Communication Technology for Embedded Systems (IC-ICTES)",,,,,2019,Apr.
"高橋篤司","離散数学の応用",,"電子情報通信学会通信ソサイエティマガジンB-plus",,,"No. 48","pp. 289-292",2019,Mar.
"赤木佳乃,佐藤真平,高橋篤司","選択的な端子対接続による集合対間配線手法",,"電子情報通信学会技術研究報告",,"vol. 118","no. 457","pp. 37-42",2019,Feb.
"佐々栄治郎,佐藤真平,高橋篤司","一般同期性能を向上させる遅延最適化に関する検討",,"電子情報通信学会技術研究報告",,"vol. 118","no. 430","pp. 1-6",2019,Jan.
"東梨奈,小平行秀,松井知己,高橋篤司,児玉親亮,野嶋茂樹","0-1二次計画法によるプロセスばらつきを考慮したモデルベースマスク補正手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2018-70)",,"Vol. 118","No. 334","pp. 209-214",2018,Dec.
"大和田真由,和田邦彦,赤木佳乃,佐藤真平,高橋篤司","集合対間配線問題ソルバと引きはがし再配線のADC2018問題への適用",,"情報処理学会研究報告",,"Vol. 2018-SLDM-185","No. 13","pp. 1-6",2018,Dec.
"赤木佳乃,大和田真由,和田邦彦,佐藤真平,高橋篤司","集合対間配線手法のADC2018への適用に関する一考察",,"情報処理学会研究報告",,"Vol. 2018-SLDM-185","No. 12","pp. 1-6",2018,Dec.
"和田邦彦,大和田真由,赤木佳乃,佐藤真平,高橋篤司","ADC2018問題の自動生成手法に関する一検討",,"情報処理学会研究報告",,"Vol. 2018-SLDM-185","No. 11","pp. 1-4",2018,Dec.
"西原  明法,篭橋雄二,スチュワート・デービッド,高橋篤司,山田 明","6大学工学系助教意識調査","日本教育工学会 第34回全国大会","日本教育工学会全国大会講演論文集","日本教育工学会","Vol. 34",,"pp. 853-854",2018,Sept.
"高橋秀和,佐藤真平,高橋篤司","人物認識のためのHOGをベースとした低次元特徴量の検討","DAシンポジウム2018 ?システムとLSIの設計技術?","DAシンポジウム2018 論文集，情報処理学会シンポジウムシリーズ","一般社団法人 情報処理学会","Vol. 2018",,"pp. 45-50",2018,Aug.
"Atsushi Takahashi,Shimpei Sato,Hiroki Ogura,Yu-Min Sung,Ting-Chi Wang","Pattern Similarity Metrics for Layout Pattern Classification and their Validity Analysis by Lithographic Responses",,"Proc. 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)",,,,"pp. 494-497",2018,July
"Atsushi Takahashi","Routing Algorithms for VLSI and their Theoretical Background","11th International Conference on Embedded Systems and Intelligent Technology (ICESIT 2018) - The Ninth International Conference on Information and Communication Technology for Embedded Systems (IC-ICTES 2018)",,,,,,2018,May
"Kano Akagi,Shimpei Sato,Atsushi Takahashi","Target Pin-Pair Selection Algorithm Using Minimum Maximum-Edge-Weight Matching for Set-Pair Routing",,"Proc. the 21st Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2018)",,,,"pp. 337-342",2018,Mar.
"Atsushi Takahashi","Routing Algorithms - from classic to advanced -","IEEE CASS Central China Workshop",,,,,,2017,Nov.
"赤木佳乃,佐藤真平,高橋篤司","集合対間配線における目標端子対選択法に関する一検討","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2017-59)",,"Vol. 117","No. 273","pp. 235-240",2017,Nov.
"高橋篤司","FR とファンダム・レビュー",,"電子情報通信学会 基礎・境界ソサイエティ Fundamentals Review",,"Vol. 11","No. 2",,2017,Oct.
"西原明法,スチュワート デービッド,篭橋 雄二,高橋 篤司,山田 明","6大学人財交流による教員育成の推進","日本教育工学会 第33回全国大会","日本教育工学会 第33回全国大会 講演論文集",,,,,2017,Sept.
"Atsushi Takahashi","Routing Algorithms - from classic to advanced -","2017 Taiwan and Japan Conference on Circuits and Systems (TJCAS)",,,,,,2017,Aug.
"Takeshi Ihara,Toshiyuki Hongo,Atsushi Takahashi,Chikaaki Kodama","A Routing Method Using Directed Grid-Graph for Self-Aligned Quadruple Patterning",,"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",,"Vol. E100-A","No. 7","pp. 1473-1480",2017,July
"Kano Akagi,Shimpei Sato,Atsushi Takahashi","An Idea for Maximizing Target Pin-Pair Connections in Set-Pair Routing",,"Proc. the 32nd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2017)",,,,"pp. 62-65",2017,July
"右近祐太,佐藤真平,高橋篤司","演算器の可変レイテンシ化による処理性能と回路面積のトレードオフに関する評価","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2017-26)",,"Vol. 117","No. 97","pp. 119-124",2017,June
"赤木佳乃,佐藤真平,高橋篤司","目標端子対接続の実現を目指す集合対間配線アルゴリズム","第30回 回路とシステムワークショップ","第30回 回路とシステムワークショップ 論文集",,,,"pp. 180-185",2017,May
"高橋 篤司","IEEE CEDA日本チャプター発足とその役割","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2017-59)",,"Vol. 117","No. 17","pp. 31-34",2017,May
"Ahmed Awad,Atsushi Takahashi,Satoshi Tanaka,Chikaaki Kodama","A Fast Process-Variation-Aware Mask Optimization Algorithm With a Novel Intensity Modeling",,"IEEE Transactions on Very Large Scale Integration (VLSI) Systems",,"Vol. 25","No. 3","pp. 998-1011",2017,Mar.
"杉原舜,佐藤真平,高橋篤司","単層プリント基板における目標等長配線を実現するための部分配線修正手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2016-114)",,"Vol. 116","No. 478","pp. 73-78",2017,Mar.
"尾頭篤,佐藤真平,高橋篤司","LELEダブルパターニングにおけるFMアルゴリズムを用いた効率的なパターン局所修正手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2016-113)",,"Vol. 116","No. 478","pp. 67-72",2017,Mar.
"半田昌平,佐藤真平,高橋篤司","TPLのための半正定値計画緩和に基づくレイアウト分割手法のポリゴン集合クラスタリングによる高速化","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2016-111)",,"Vol. 116","No. 478","pp. 55-60",2017,Mar.
"高橋篤司","グラフは難だが役に立つ",,"電子情報通信学会 2017年総合大会 講演論文集 (AS-1-4)",,"Vol. A",,"pp. S6-S7",2017,Mar.
"Ahmed Awad,Atsushi Takahashi,Satoshi Tanaka,Chikaaki Kodama","Intensity Difference Map (IDM) Accuracy Analysis for OPC Efficiency Verification and Further Enhancement",,"IPSJ Trans. on System LSI Design Methodology",,"Vol. 10",,"pp. 28-38",2017,Feb.
"佐藤真平,右近祐太,高橋篤司","典型的な回路を用いた近似演算における入力系列の演算精度への影響の調査","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2016-95)",,"Vol. 116","No. 415","pp. 165-170",2017,Jan.
"Ahmed Awad,Atsushi Takahashi,Chikaaki Kodama","A Fast Mask Manufacturability and Process Variation Aware OPC Algorithm with Exploiting a Novel Intensity Estimation Model",,"IEICE Trans. Fundamentals",,"Vol. E99-A","No. 12","pp. 2363-2374",2016,Dec.
"Shimpei Sato,Hiroshi Nakatsuka,Atsushi Takahashi","Performance Improvement of General-Synchronous Circuits by Variable Latency Technique using Dynamic Timing-Error Detection",,"Proc. the 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016)",,,,"pp. 60-65",2016,Oct.
"Yukihide Kohira,Atsushi Takahashi,Tomomi Matsui,Chikaaki Kodama,Shigeki Nojima,Satoshi Tanaka","Manufacturability-aware Mask Assignment in Multiple Patterning Lithography",,"Proc. the 2016 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2016)",,,,"pp. 538-541",2016,Oct.
"西原明法,篭橋雄二,高橋篤司,山田 明","6大学人財交流による共同教員育成","日本教育工学会第32回全国大会","日本教育工学会第32回全国大会",,,"  1a-B107-01",,2016,Sept.
"木村優介,佐藤真平,高橋篤司","Self-Aligned Double Patterningのための柔軟な2彩色配線法の提案",,"DAシンポジウム2016 論文集，情報処理学会シンポジウムシリーズ",,"Vol. 2016","No. 6","pp. 26-31",2016,Sept.
"半田昌平,高橋篤司,中田和秀,松井知己","半正定値計画緩和に基づく擬似スティッチを用いたTPLのためのレイアウト分割手法",,"第29回 回路とシステムワークショップ 論文集",,,,"pp. 214-219",2016,May
"Ahmed Awad,Atsushi Takahashi","A Lithographic Mask Manufacturability and Pattern Fidelity Aware OPC Algorithm",,"Proc. International Symposium on VLSI Design, Automation and Test (VLSI-DAT 2016)",,,,"pp. 1-4",2016,Apr.
"半田昌平,高橋篤司,中田和秀,松井知己","半正定値計画緩和に基づくMPLレイアウト分割のための補正項",,"電子情報通信学会 2016年総合大会 講演論文集 (A-6-12)",,"Vol. A",,"p. 86",2016,Mar.
"本江俊幸,高橋篤司","Self-Aligned Quadruple Patterningのための3色グリッド上の異色ネットを考慮した配線手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2015-135)",,"Vol. 115","No. 465","pp. 137-142",2016,Mar.
"Takeshi Ihara,Toshiyuki Hongo,Atsushi Takahashi,Chikaaki Kodama","Grid-based Self-Aligned Quadruple Patterning Aware Two Dimensional Routing Pattern",,"Proc.  Design, Automation and Test in Europe (DATE 2016)",,,,"pp. 241-244",2016,Mar.
"中塚裕志,高橋篤司","動的タイミングエラー検出を用いた可変レイテンシ化による一般同期式回路の高性能化","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2015-140)",,"Vol. 115","No. 465","pp. 167-172",2016,Mar.
"Ahmed Awad,Atsushi Takahashi,Chikaaki Kodama","A Fast Manufacturability Aware Optical Proximity Correction (OPC) Algorithm with Adaptive Wafer Image Estimation",,"Proc.  Design, Automation and Test in Europe (DATE 2016)",,,,"pp. 49-54",2016,Mar.
"Yukihide Kohira,Chikaaki Kodama,Tomomi Matsui,Atsushi Takahashi,Shigeki Nojima,Satoshi Tanaka","Yield-aware mask assignment by positive semidefinite relaxation in triple patterning using cut process",,"Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3)",,"Vol. 15","No. 2","pp. 1-7",2016,Mar.
"Pattanusorn, W.,Nilkhamhang, I.,Kittipiyakul, S.,Ekkachai, K.,Atsushi Takahashi","Passenger estimation system using Wi-Fi probe request",,"7th International Conference on Information Communication Technology for Embedded Systems 2016, IC-ICTES 2016",,,,"pp. 67-72",2016,
"井原岳志,高橋篤司","Self-Aligned Quadruple Patterningのための3次配線アルゴリズムを用いた効率的な配線生成手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2015-53)",,"Vol. 115","No. 338","pp. 93-98",2015,Dec.
"Yuta Nakatani,Atsushi Takahashi","A Length Matching Routing Algorithm for Set-Pair Routing Problem",,"IEICE Trans. Fundamentals",,"Vol. E98-A","No. 12","pp. 2565-2571",2015,Dec.
"井原岳志,本江俊幸,高橋篤司","Self-Aligned Quadruple Patterningのための配線パターンの効率的な生成手法",,"DAシンポジウム2015 論文集，情報処理学会シンポジウムシリーズ",,"Vol. 2015",,"pp. 125-130",2015,Aug.
"Ahmed Awad,Atsushi Takahashi","Mask Manufacturability Aware Post OPC Algorithm For Optical Lithography",,"Proc. DA Symposium 2015, IPSJ Symposium Series",,"Vol. 2015",,"pp. 119-124",2015,Aug.
"小平行秀,児玉親亮,松井知己,高橋篤司,野嶋茂樹,田中聡","マスク位置ずれに対する耐性を持つLELECUTトリプルパターニングのためのマスク割り当て手法",,"次世代リソグラフィワークショップ予稿集 (NGL2015)",,,,"pp. 35-36",2015,July
"Takeshi Ihara,Atsushi Takahashi,Chikaaki Kodama","Effective two-dimensional pattern generation for self-aligned double patterning",,"Proc. IEEE International Symposium on Circuits and Systems (ISCAS 2015)",,,,"pp. 2141-2144",2015,May
"本江俊幸,高橋篤司","折れ曲がり制約を含む配線問題のNP完全性","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2015-3)",,"Vol. 115","No. 21","pp. 13-18",2015,May
"Chikaaki Kodama,Hirotaka Ichikawa,Koichi Nakayama,Fumiharu Nakajima,Shigeki Nojima,Toshiya Kotani,Takeshi Ihara,Atsushi Takahashi.","Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods",,"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)",,"Vol. 34","No. 5","pp. 753-765",2015,May
"高橋紀之,井原岳志,高橋篤司","側壁プロセス配線におけるカットパターン削減手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2014-154)",,"Vol. 114","No. 476","pp. 7-12",2015,Mar.
"田中雄一郎,高橋篤司","位相的な配線可能性を考慮した高速なナンバーリンク解法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2014-155)",,"Vol. 114","No. 476","pp. 13-18",2015,Mar.
"Ahmed Awad,Atsushi Takahashi","A Fast Lithographic Mask Correction Algorithm","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2014-153)",,"Vol. 114","No. 476","pp. 1-6",2015,Mar.
"Takeshi Ihara,Atsushi Takahashi,Chikaaki Kodama","Rip-up and Reroute based Routing Algorithm for Self-Aligned Double Patterning",,"Proc. the 19th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2015)",,,,"pp. 83-88",2015,Mar.
"Yukihide Kohira,Chikaaki Kodama,Tomomi Matsui,Atsushi Takahashi,Shigeki Nojima,Satoshi Tanaka","Yield-aware mask assignment using positive semidefinite relaxation in LELECUT triple patterning",,"Proc. SPIE 9427, Design-Process-Technology Co-optimization for Manufacturability IX, 94270B",,,,"  1-9",2015,Mar.
"大月郷史,高橋篤司","エラー検出回復方式を導入した乗算器の性能検証","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2014-181)",,"Vol. 114","No. 476","pp. 159-164",2015,Mar.
"中谷勇太,高橋篤司","集合対間配線における配線付け替えのためのゼロ閉路探索手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2014-156)",,"Vol. 114","No. 476","pp. 19-24",2015,Mar.
"Yukihide Kohira,Tomomi Matsui,Yoko Yokoyama,Chikaaki Kodama,Atsushi Takahashi,Shigeki Nojima,Satoshi Tanaka","Fast Mask Assignment using Positive Semidefinite Relaxation in LELECUT Triple Patterning Lithography",,"Proc. Asia and South Pacific Design Automation Conference 2015 (ASP-DAC 2015)",,,,"pp. 665-670",2015,Jan.
"Julkananusar, A.,Nilkhamhang, I.,Vanijjirattikhan, R.,Atsushi Takahashi","Quadrotor tuning for attitude control based on PID controller using fictitious reference iterative tuning (FRIT)",,"2015 6th International Conference on Information and Communication Technology for Embedded Systems, IC-ICTES 2015",,,,,2015,
"Yukihide Kohira,Atsushi Takahashi","2-SAT Based Linear Time Optimum Two-Domain Clock Skew Scheduling in General-Synchronous Framework",,"IEICE Trans. Fundamentals",,"Vol. E97-A","No. 12","pp. 2459-2466",2014,Dec.
"Yiqiang Sheng,Atsushi Takahashi","A Novel High-Performance Heuristic Algorithm with Application to Physical Design Optimization",,"IEICE Trans. Fundamentals",,"Vol. E97-A","No. 12","pp. 2418-2426",2014,Dec.
"中谷勇太,高橋篤司","集合対間配線における総配線長および配線長差の削減手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2014-87)",,"Vol. 114","No. 328","pp. 111-116",2014,Nov.
"Atsushi Takahashi,Ahmed Awad,Yukihide Kohira,Tomomi Matsui,Chikaaki Kodama,Shigeki Nojima,Satoshi Tanaka","[Invited] Multi Patterning Techniques for Manufacturability Enhancement in Optical Lithography",,"Proc. the 2014 International Conference on Integrated Circuits, Design, and Verification (ICDV 2014)",,,,"pp. 117-122",2014,Nov.
"Ahmed Awad,Atsushi Takahashi,Satoshi Tanaka,Chikaaki Kodama","A Fast Process Variation and Pattern Fidelity Aware Mask Optimization Algorithm",,"Proc. IEEE/ACM 2014 International Conference on Computer-Aided Design (ICCAD 2014)",,,,"pp. 238-245",2014,Nov.
"Tomomi Matsui,Yukihide Kohira,Chikaaki Kodama,Atsushi Takahashi","Positive Semidefinite Relaxation and Approximation Algorithm for Triple Patterning Lithography","the 25th International Symposium on Algorithms and Computation (ISAAC 2014)","Algorithms and Computation, Lecture Notes in Computer Science",,"  LNCS 8889",,"pp. 365?375",2014,Nov.
"Ahmed Awad,Atsushi Takahashi,Satoshi Tanaka,Chikaaki Kodama","A Process Variability Band Area Reduction Algorithm For Optical Lithography",,"Proc. the 2014 IEICE Society Conference (A-3-6)",,"Vol. A",,"p. 50",2014,Sept.
"佐藤泰介,高橋篤司,伊東利哉,上野修一","情報基礎数学",,,"オーム社",,,,2014,Sept.
"田中雄一郎,高橋篤司","領域分割を用いたCHORD-LAST法に基づくナンバーリンク解法",,"DAシンポジウム2014 論文集，情報処理学会シンポジウムシリーズ",,"Vol. 2014",,"pp. 221-226",2014,Aug.
"Ahmed Awad,Atsushi Takahashi,Satoshi Tanaka,Chikaaki Kodama","Mask Optimization With Minimal Number of Convolutions Using Intensity Difference Map",,"Proc. DA Symposium 2014, IPSJ Symposium Series",,"Vol. 2014",,"pp. 145-150",2014,Aug.
"Ahmed Awad,Atsushi Takahashi,Satoshi Tanaka,Chikaaki Kodama","A New Intensity Based Edge Placement Error Optimization Algorithm for Optical Lithography",,"Proc. the 27th Workshop on Circuits and Systems",,,,"pp. 422-427",2014,Aug.
"小平行秀,横山陽子,児玉親亮,高橋篤司,野嶋茂樹,田中聡","LELEダブルパターニングのための歩留まりを考慮した高速マスク割り当て手法",,"次世代リソグラフィワークショップ予稿集 (NGL2014)",,,,"pp. 41-42",2014,July
"小平行秀,松井知己,横山陽子,児玉親亮,高橋篤司,野嶋茂樹,田中聡","半正定値緩和法を用いたLELECUTトリプルパターニングのためのレイアウト分割手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2014-6)",,"Vol. 114","No. 59","pp. 27-32",2014,May
"宮辺祐太郎,高橋篤司,松井知己,小平行秀,横山陽子","ダブルパターニングにおけるリソグラフィECOのためのパターン局所修正法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2013-149)",,"Vol. 113","No. 454","pp. 87-92",2014,Mar.
"Yukihide Kohira,Yoko Yokoyama,Chikaaki Kodama,Atsushi Takahashi,Shigeki Nojima,Satoshi Tanaka","Yield-aware decomposition for LELE double patterning",,"Proc. SPIE   9053, Design-Process-Technology Co-optimization for Manufacturability VIII, 90530T",,,,"  1-10",2014,Mar.
"Yoko Yokoyama,Keishi Sakanushi,Yukihide Kohira,Atsushi Takahashi,Chikaaki Kodama,Satoshi Tanaka,Shigeki Nojima","Localization concept of re-decomposition area to fix hotspots for LELE process",,"Proc. SPIE   9053, Design-Process-Technology Co-optimization for Manufacturability VIII, 90530V",,,,"  1-8",2014,Mar.
"井原岳志,高橋篤司,児玉親亮","側壁ダブルパターニングのための修正2色グリッド配線法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2013-150)",,"Vol. 113","No. 454","pp. 93-98",2014,Mar.
"山本祐作,高橋篤司","集合対間配線に対する配線長差削減アルゴリズムの改良","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2013-142)",,"Vol. 113","No. 454","pp. 49-54",2014,Mar.
"Yukihide Kohira,Atsushi Takahashi","2-SAT based Linear Time Optimum Two-Domain Clock Skew Scheduling",,"Proc. Asia and South Pacific Design Automation Conference 2014 (ASP-DAC 2014)",,,,"pp. 173-178",2014,Jan.
"大月郷史,高橋篤司","FPGA上に実現した可変レイテンシ技術を用いた乗算器の性能検証",,"DAシンポジウム2013 論文集，情報処理学会シンポジウムシリーズ",,"Vol. 2013","No. 3","pp. 157-162",2013,Aug.
"Yiqiang Sheng,Atsushi Takahashi","A New Variation of Adaptive Simulated Annealing for 2D/3D Packing Optimization",,"IPSJ Trans. on System LSI Design Methodology",,"Vol. 6",,"pp. 94-100",2013,Aug.
"Yukihide Kohira,Yoko Takekawa,Chikaaki Kodama,Atsushi Takahashi,Shigeki Nojima,Satoshi Tanaka","Overlap Area Maximization in Stitch Selection for LELE Double Patterning",,"Proc. the 26th Workshop on Circuits and Systems",,,,"pp. 466-471",2013,July
"Yukihide Kohira,Yoko Takekawa,Chikaaki Kodama,Atsushi Takahashi,Shigeki Nojima,Satoshi Tanaka","Minimum Cost Stitch Selection in LELE Double Patterning","Design for Manufacturability and Yield 2013 (DFM&Y2013)",,,,,,2013,June
"Yoko Takekawa,Chikaaki Kodama,Atsushi Takahashi,Yukihide Kohira,Satoshi Tanaka,Keishi Sakanushi,Jiro Higuchi,Shigeki Nojima","A Study of Robust Stitch Design for Litho-etch-litho-etch Double Patterning","Design for Manufacturability and Yield 2013 (DFM&Y2013)",,,,,,2013,June
"篠田享佑,高橋篤司","単層プリント基板のための各ネットの目標配線長達成性を考慮した配線手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2012-149)",,"Vol. 112","No. 451","pp. 77-82",2013,Mar.
"安藤健太,高橋篤司","エラー検出回復方式を用いた可変レイテンシ回路のための高速な性能見積もり手法","システムLSI設計技術研究会","情報処理学会研究報告",,"Vol. 2013-SLDM-160","No. 16","pp. 1-6",2013,Mar.
"Atsushi Takahashi","Dawn of Computer-aided Design - from Graph-theory to Place and Route -",,"Proc. ACM International Symposium on Physical Design  (ISPD 2013)",,,,"p. 58",2013,Mar.
"篠田享佑,高橋篤司","指定長幹配線問題において配線長を調整する領域に関する一考察",,"電子情報通信学会 2013年総合大会 講演論文集 (A-3-6)",,"Vol. A",,"p. 66",2013,Mar.
"Chikaaki Kodama,Hirotaka Ichikawa,Koichi Nakayama,Toshiya Kotani,Shigeki Nojima,Shoji Mimotogi,Shinji Miyamoto,Atsushi Takahashi","Self-Aligned Double and Quadruple Patterning Aware Grid Routing with Hotspots Control",,"Proc. Asia and South Pacific Design Automation Conference 2013 (ASP-DAC 2013)",,,,"pp. 267-272",2013,Jan.
"秋田大,安藤健太,高橋篤司","動的遅延分布の高速な見積もり手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2012-55)",,"Vol. 112","No. 245","pp. 83-88",2012,Oct.
"Yiqiang Sheng,Atsushi Takahashi","A Simulated Annealing Based Approach to Integrated Circuit Layout Design",,"Simulated Annealing - Single and Multiple Objective Problems","InTech",,,"pp. 239-260",2012,Oct.
"小平行秀,高橋篤司","一般同期方式における最適2クラスタ分割手法",,"第25回 回路とシステムワークショップ論文集",,,,"pp. 178-183",2012,July
"高橋篤司","遅延ばらつき適応回路：遅延ばらつき状況下の高性能回路",,"第25回 回路とシステムワークショップ論文集",,,,"pp. 184-189",2012,July
"篠田享佑,小平行秀,高橋篤司","単層プリント基板のための各ネットの配線長達成性を考慮した等長配線手法",,"電子情報通信学会 2012年総合大会 講演論文集 (A-3-3)",,"Vol. A",,"p. 87",2012,Mar.
"Kenta Ando,Atsushi Takahashi","Performance Evaluation of Various Configuration of Adder in Variable Latency Circuits with Error Detection/Correction Mechanism",,"Proc. the 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012)",,,,"pp. 549-554",2012,Mar.
"Yiqiang Sheng,Atsushi Takahashi,Shuichi Ueno","2-Stage Simulated Annealing with Crossover Operator for 3D-Packing Volume Minimization",,"Proc. the 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012)",,,,"pp. 227-232",2012,Mar.
"右近祐太,安藤健太,高橋篤司","FPGA上に実現した可変レイテンシ回路の性能評価","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2011-141)",,"Vol. 111","No. 450","pp. 127-132",2012,Mar.
"Yukihide Kohira,Atsushi Takahashi","An Any-Angle Routing Method using Quasi-Newton Method",,"Proc. Asia and South Pacific Design Automation Conference 2012 (ASP-DAC 2012)",,,,"pp. 145-150",2012,Jan.
"Kyosuke Shinoda,Yukihide Kohira,Atsushi Takahashi","Single-Layer Trunk Routing Using Minimal 45-Degree Lines",,"IEICE Trans. Fundamentals",,"Vol. E94-A","No. 12","pp. 2510-2518",2011,Dec.
"Atsushi Takahashi","Foreword",,"IEICE Trans. Fundamentals",,"Vol. E94-A","No. 12","p. 2481",2011,Dec.
"Atsushi Takahashi","Adaptive Computing Oriented Circuit Synthesis",,"Proc. Ambient GCOE International Workshop on System LSI : Ambient SoC - Now and Beyond",,,,"p. 6",2011,Nov.
"山本祐作,高橋篤司","PCB一層配線における集合対間配線のフローを用いた配線長差削減アルゴリズム","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2011-87)",,"Vol. 111","No. 324","pp. 203-208",2011,Nov.
"Yiqiang Sheng,Atsushi Takahashi,Shuichi Ueno","An Improved Simulated Annealing for 3D Packing with Sequence Triple and Quintuple Representations","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2011-88)",,"Vol. 111","No. 324","pp. 209-214",2011,Nov.
"Yiqiang Sheng,Atsushi Takahashi,Shuichi Ueno","RRA-Based Multi-Objective Optimization to Mitigate the Worst Cases of Placement",,"Proc. IEEE 9th International Conference on ASIC (ASICON 2011)",,,,"pp. 357-360",2011,Oct.
"小平行秀,高橋篤司","準ニュートン法を用いた自由角度配線のための逐次改善手法",,"電子情報通信学会 2011年ソサイエティ大会 講演論文集 (A-3-20)",,"Vol. A",,"p. 94",2011,Sept.
"高橋篤司","集合対間配線問題に関する一考察","VLSI設計技術研究会","電子情報通信学会技術報告書 (VLD2011-44)",,"Vol. 111","No. 216","pp. 23-28",2011,Sept.
"Yiqiang Sheng,Atsushi Takahashi,Shuichi Ueno","MSA: Mixed Stochastic Algorithm for Placement with Larger Solution Space","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2011-42)",,"Vol. 111","No. 216","pp. 11-16",2011,Sept.
"Yiqiang Sheng,Atsushi Takahashi,Shuichi Ueno","A Stochastic Optimization Method to Solve General Placement Problem Effectively",,"Proc. DA Symposium 2011, IPSJ Symposium Series",,"Vol. 2011","No. 5","pp. 27-32",2011,Aug.
"小平行秀,高橋篤司","準ニュートン法を用いた自由角度配線手法",,"第24回 回路とシステムワークショップ 論文集",,,,"pp. 425-430",2011,Aug.
"安藤健太,高橋篤司","エラー検出回復方式における様々な加算器の性能評価","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2011-33)",,"Vol. 111","No. 103","pp. 147-152",2011,July
"Yiqiang Sheng,Atsushi Takahashi,Shuichi Ueno","Relay-Race Algorithm: A Novel Heuristic Approach to VLSI/PCB Placement",,"Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2011)",,,,"pp. 96-101",2011,July
"河野祐貴,高島康裕,高橋篤司","最小総変位配置実現問題に対し効率的な位相変更手法CRP法の提案","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2010-138)",,"Vol. 110","No. 432","pp. 129-134",2011,Mar.
"井上雅文,右近祐太,高橋篤司","ゲートレベルシミュレーションによるエラー検出・回復方式回路の評価","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2010-141)",,"Vol. 110","No. 432","pp. 147-152",2011,Mar.
"右近祐太,井上雅文,高橋篤司,谷口研二","FPGA上に実現した可変レイテンシ回路の動作検証","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2010-142)",,"Vol. 110","No. 432","pp. 153-158",2011,Mar.
"Yukihide Kohira,Atsushi Takahashi","CAFE router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles",,"IEICE Trans. Fundamentals",,"Vol. E93-A","No. 12","pp. 2380-2388",2010,Dec.
"高橋篤司","［招待講演］VLSI設計自動化の現状と将来展望",,"応用物理学会分科会シリコンテクノロジー",,,"No. 128","pp. 42-43",2010,Nov.
"Kyosuke Shinoda,Yukihide Kohira,Atsushi Takahashi","Single-Layer Trunk Routing Using 45-Degree Lines within Critical Areas for PCB Routing",,"Proc. the 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2010)",,,,"pp. 278-283",2010,Oct.
"河野祐貴,高島康裕,高橋篤司","総変位最小配置のための高速位相変更手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2010-51)",,"Vol. 110","No. 210","pp. 55-60",2010,Sept.
"小平行秀,高橋篤司","一般同期方式におけるクラスタ分割に基づくクロック木の性能評価",,"電子情報通信学会 2010ソサイエティ大会 講演論文集 (A-3-1)",,"Vol. A",,"p. 63",2010,Sept.
"篠田享佑,小平行秀,高橋篤司","単層プリント基板配線のための高混雑度領域特定手法",,"電子情報通信学会 2010ソサイエティ大会 講演論文集 (A-3-4)",,"Vol. A",,"p. 66",2010,Sept.
"井上雅文,右近祐太,高橋篤司,谷口研二","エラー検出回復方式回路の回路構成と性能に関するシミュレーション評価",,"DAシンポジウム2010 論文集, 情報処理学会シンポジウムシリーズ",,"Vol. 2010","No. 7","pp. 123-128",2010,Sept.
"小平行秀,高橋篤司","［招待講演］PCB配線設計のための一層複線指定長配線手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2010-47)",,"Vol. 110","No. 210","pp. 31-36",2010,Sept.
"Atsushi Takahashi","Approaches for Improving Synchronous Circuit Performance","Physical Design Issues for Highly Integrated LSI and SiP, IEEE Circuits and Systems Society Kansai Chapter",,,,,,2010,July
"篠田享佑,小平行秀,高橋篤司","単層プリント基板配線のための効率的な高混雑度領域特定および45度線による混雑度緩和法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2010-9)",,"Vol. 110","No. 36","pp. 79-84",2010,May
"木下昌紀,富岡洋一,高橋篤司","2層BGAパッケージのための詳細ビア配置手法の評価","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2009-117)",,"Vol. 109","No. 462","pp. 109-114",2010,Mar.
"高橋伸嘉,富岡洋一,小平行秀,高橋篤司","入力ベクトルと回路の内部状態を考慮したピーク電力高速見積もり手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2009-115)",,"Vol. 109","No. 462","pp. 97-102",2010,Mar.
"右近祐太,井上雅文,高橋篤司,谷口研二","エラー検出回復方式における加算器の性能評価","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2009-121)",,"Vol. 109","No. 462","pp. 133-138",2010,Mar.
"小平行秀,高橋篤司","一般同期方式における消費電力を抑えたクロック木構成のためのクラスタ分割法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2009-119)",,"Vol. 109","No. 462","pp. 121-126",2010,Mar.
"Yukihide Kohira,Atsushi Takahashi","CAFE router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles",,"Proc. Asia and South Pacific Design Automation Conference 2010 (ASP-DAC 2010)",,,,"pp. 281-286",2010,Jan.
"Nobuyoshi Takahashi,Atsushi Takahashi","Fast Estimation of Peak Power by Appropriate Input Vector Selection","Student Forum at Asia and South Pacific Design Automation Conference 2010(ASP-DAC 2010)",,,,,,2010,Jan.
"Yukihide Kohira,Suguru Suehiro,Atsushi Takahashi","A Fast Longer Path Algorithm for Routing Grid with Obstacles using Biconnectivity based Length Upper Bound",,"IEICE Trans. Fundamentals",,"Vol. E92-A","No. 12","pp. 2971-2978",2009,Dec.
"Yoichi Tomioka,Yoshiaki Kurata,Yukihide Kohira,Atsushi Takahashi","MILP-based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages",,"IEICE Trans. Fundamentals",,"Vol. E92-A","No. 12","pp. 2998-3006",2009,Dec.
"Nobuyoshi Takahashi,Atsushi Takahashi","Fast Estimation of Peak Power by Appropriate Input Vector Selection","The 6th IEEE Tokyo Young Researchers Workshop",,,,,,2009,Dec.
"右近祐太,高橋篤司,谷口研二","［ポスター講演］加算器におけるクロック周期に応じた遅延エラー率の評価","集積回路研究会","電子情報通信学会技術研究報告 (ICD2009-91)",,"Vol. 109","No. 336","pp. 77-81",2009,Dec.
"Atsushi Takahashi","New Design Methodologies for Synchronous Circuits",,"Special Papers of IEEJ the 2009 International Analog VLSI Workshop",,,,"pp. I2-1-I2-4",2009,Nov.
"Atsushi Takahashi","Recent Advances in Routing Control Technology",,"Proc. Japan-Taiwan Semiconductor Electronic Design Automation (EDA) Science and Technology Symposium",,,,"pp. 143-150",2009,Sept.
"木下昌紀,富岡洋一,高橋篤司","2層BGAパッケージにおける配線混雑度低減のための詳細ビア配置手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2009-30)",,"Vol. 109","No. 201","pp. 7-12",2009,Sept.
"小平行秀,高橋篤司","1層複線配線問題における幹配線を生成するための壁生成法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2009-31)",,"Vol. 109","No. 201","pp. 13-18",2009,Sept.
"小平行秀,高橋篤司","障害物を含む1層配線領域のための領域分割によるリバー配線手法",,"電子情報通信学会 2009ソサイエティ大会 講演論文集 (A-3-9)",,"Vol. A",,"p. 58",2009,Sept.
"Yoichi Tomioka,Atsushi Takahashi","Top Layer Plating Lead Maximization for BGA Packages",,"Proc. the 2009 IEICE Society Conference (A-3-10)",,"Vol. A",,"p. 59",2009,Sept.
"高橋伸嘉,富岡洋一,小平行秀,高橋篤司","入力ベクトルの適切な選択によるピーク電力高速見積り手法",,"DAシンポジウム2009論文集, 情報処理学会シンポジウムシリーズ",,"Vol. 2009","No. 7","pp. 13-18",2009,Aug.
"篠田享佑,小平行秀,高橋篤司","プリント基板のための45度線による混雑度緩和を利用した配線手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2009-23,CAS2009-18,SIP2009-35)",,"Vol. 109","No. 111","pp. 97-102",2009,July
"Yoichi Tomioka,Atsushi Takahashi","Routability Driven Via Assignment Method for 2-Layer Ball Grid Array Packages",,"IEICE Trans. Fundamentals",,"Vol. E92-A","No. 6","pp. 1433-1441",2009,June
"井上雅文,富岡洋一,小平行秀,高橋篤司","パス長制限付き点集合に対する配線木構成手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2009-4)",,"Vol. 109","No. 34","pp. 31-36",2009,May
"Yukihide Kohira,Shuhei Tani,Atsushi Takahashi","Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework",,"IEICE Trans. Fundamentals",,"Vol. E92-A","No. 4","pp. 1106-1114",2009,Apr.
"末廣傑,小平行秀,高橋篤司","障害物を含む配線領域における並走配線最長化手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2008-137)",,"Vol. 108","No. 487","pp. 59-64",2009,Mar.
"河野祐貴,高島康裕,高橋篤司","最小総変位配置実現問題における高速最適化手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2008-138)",,"Vol. 108","No. 487","pp. 65-70",2009,Mar.
"谷修平,小平行秀,高橋篤司","クロック周期短縮のための挿入遅延量を抑えた回路への遅延挿入法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2008-135)",,"Vol. 108","No. 487","pp. 53-58",2009,Mar.
"橋本浩良,小平行秀,高橋篤司","EDAツールを用いた低コスト一般同期クロックツリー合成手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2008-134)",,"Vol. 108","No. 487","pp. 47-52",2009,Mar.
"Yoshiaki Kurata,Yoichi Tomioka,Yukihide Kohira,Atsushi Takahashi","A Routing Method based on Nearest Via Assignment for 2-Layer Ball Grid Array Packages",,"Proc. the 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009)",,,,"pp. 307-312",2009,Mar.
"Shun Gokita,Yukihide Kohira,Atsushi Takahashi","A Fast Approximation Method of Maximum Operation in Statistical Static Timing Analysis for Achieving Specified Yield",,"Proc. the 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009)",,,,"pp. 364-369",2009,Mar.
"Yukihide Kohira,Suguru Suehiro,Atsushi Takahashi","A Fast Longer Path Algorithm for Routing Grid with Obstacles using Biconnectivity based Length Upper Bound",,"Proc. Asia and South Pacific Design Automation Conference 2009 (ASP-DAC 2009)",,,,"pp. 600-605",2009,Jan.
"Yoichi Tomioka,Atsushi Takahashi","A Semi-Monotonic Routing Method for Fanin Type Ball Grid Array Packages",,"Proc. the 2008 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2008)",,,,"pp. 1550-1553",2008,Dec.
"Yosuke Takahashi,Yukihide Kohira,Atsushi Takahashi","A Fast Clock Scheduling for Peak Power Reduction in LSI",,"IEICE Trans. Fundamentals",,"Vol. E91-A","No. 12","pp. 3803-3811",2008,Dec.
"Masato Inagi,Yasuhiro Takashima,Yuichi Nakamura,Atsushi Takahashi","Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems",,"IEICE Trans. Fundamentals",,"Vol. E91-A","No. 12","pp. 3539-3547",2008,Dec.
"Yukihide Kohira,Shuhei Tani,Atsushi Takahashi","Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework",,"Proc. the 2008 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2008)",,,,"pp. 1680-1683",2008,Dec.
"小平行秀,高橋篤司","CAFE router: 障害物を含む領域における連結度を考慮した複線配線手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2008-72,DC2008-40)",,"Vol. 108","No. 298","pp. 73-78",2008,Nov.
"Yukihide Kohira,Atsushi Takahashi","A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework",,"IEICE Trans. Fundamentals",,"Vol. E91-A","No. 10","pp. 3030-3037",2008,Oct.
"倉田芳明,富岡洋一,小平行秀,高橋篤司","最近傍ビア配置に基づく2層BGAパッケージ自動配線手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2008-55)",,"Vol. 108","No. 224","pp. 49-54",2008,Sept.
"五木田駿,小平行秀,高橋篤司","統計的静的遅延解析における回路の指定歩留まりを達成する最大値見積もり手法",,"DAシンポジウム2008論文集, 情報処理学会シンポジウムシリーズ",,"Vol. 2008","No. 7","pp. 193-198",2008,Aug.
"Masato Inagi,Yasuhiro Takashima,Yuichi Nakamura,Atsushi Takahashi","ILP-Based Optimization of Time-Multiplexed I/O Assignment for Multi-FPGA Systems",,"Proc. the 2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008)",,,,"pp. 1800-1803",2008,May
"小平行秀,谷修平,高橋篤司","遅延挿入量最小化のためのクロックスケジューリングと遅延挿入手法",,"第21回 回路とシステム軽井沢ワークショップ 論文集",,,,"pp. 629-634",2008,Apr.
"小平行秀,末廣傑,高橋篤司","障害物を含む領域における連結度を考慮した配線長見積もりを用いた最長配線手法",,"第21回 回路とシステム軽井沢ワークショップ 論文集",,,,"pp. 569-574",2008,Apr.
"佐藤直,富岡洋一,高橋篤司","2層BGAパッケージにおけるメッキ引き出し配線手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2007-154)",,"Vol. 107","No. 507","pp. 61-66",2008,Mar.
"末廣傑,小平行秀,高橋篤司","障害物を含む領域における最大配線長見積もりに関する考察","回路とシステム研究会","電子情報通信学会技術研究報告 (CAS2007-97)",,"Vol. 107","No. 476","pp. 19-23",2008,Feb.
"石田勉,小平行秀,高橋篤司","最短パス木修正アルゴリズムの設計とその性能評価","回路とシステム研究会","電子情報通信学会技術研究報告 (CAS2007-98)",,"Vol. 107","No. 476","pp. 25-30",2008,Feb.
"Yoichi Tomioka,Atsushi Takahashi","Routability Driven Modification Method of Monotonic Via Assignment for 2-layer Ball Grid Array Packages",,"Proc. Asia and South Pacific Design Automation Conference 2008 (ASP-DAC 2008)",,,,"pp. 238-243",2008,Jan.
"Bakhtiar Affendi Rosdi,Atsushi Takahashi","Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements",,"IEICE Trans. Fundamentals",,"Vol. E90-A","No. 12","pp. 2736-2742",2007,Dec.
"Yoichi Tomioka,Atsushi Takahashi","Fast Monotonic Via Assignment Excluding Mold Gates for 2-Layer Ball Grid Array Packages",,"Proc. the 14th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2007)",,,,"pp. 192-197",2007,Oct.
"佐藤泰介,高橋篤司,伊東利哉,上野修一","情報基礎数学",,,"昭晃堂",,,,2007,Oct.
"橋本浩良,小平行秀,高橋篤司","CADツールを用いた一般同期向けクロック木合成法の改良",,"DAシンポジウム2007 論文集, 情報処理学会シンポジウムシリーズ",,"Vol. 2007","No. 7","pp. 199-204",2007,Aug.
"小平行秀,高橋篤司","一般同期方式向けレジスタ再配置手法の性能評価",,"DAシンポジウム2007 論文集, 情報処理学会シンポジウムシリーズ",,"Vol. 2007","No. 7","pp. 193-198",2007,Aug.
"富岡洋一,高橋篤司","2層BGAパッケージにおける準順行ビア割り当て手法",,"DAシンポジウム2007 論文集, 情報処理学会シンポジウムシリーズ",,"Vol. 2007","No. 7","pp. 145-150",2007,Aug.
"古屋宏基,小平行秀,高橋篤司","統計的静的遅延解析による指定良品率を達成する最大遅延値見積もり手法","システムLSI設計技術研究会","情報処理学会研究報告 (2007-SLDM-130)",,"Vol. 2007","No. 39","pp. 75-79",2007,May
"Yukihide Kohira,Atsushi Takahashi","A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework",,"Proc. the 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)",,,,"pp. 1795-1798",2007,May
"Yukihide Kohira,Atsushi Takahashi","Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization",,"IEICE Trans. Fundamentals",,"Vol. E90-A","No. 4","pp. 800-807",2007,Apr.
"Bakhtiar Affendi Rosdi,Atsushi Takahashi","Delay Balancing by Min-Cut Algorithm for Reducing the Area of Pipelined Circuits",,"Proc. the 20th Workshop on Circuits and Systems in Karuizawa",,,,"pp. 643-648",2007,Apr.
"Yosuke Takahashi,Yukihide Kohira,Atsushi Takahashi","A Fast Clock Scheduling for Peak Power Reduction in LSI",,"Proc. ACM Great Lakes Symposium on VLSI (GLSVLSI 2007)",,,,"pp. 582-587",2007,Mar.
"原田陽介,橋本浩良,小平行秀,高橋篤司","CADツールを用いた一般同期向けクロック木の一合成法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2006-127)",,"Vol. 106","No. 548","pp. 49-53",2007,Mar.
"Yoichi Tomioka,Atsushi Takahashi","Routing of Monotonic Parallel and Orthogonal Netlists for Single-Layer Ball Grid Array Packages",,"IEICE Trans. Fundamentals",,"Vol. E89-A","No. 12","pp. 3551-3559",2006,Dec.
"Bakhtiar Affendi Rosdi,Atsushi Takahashi","Multi-clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits",,"IEICE Trans. Fundamentals",,"Vol. E89-A","No. 12","pp. 3435-3442",2006,Dec.
"Bakhtiar Affendi Rosdi,Atsushi Takahashi","Replacement of Register with Delay Element for Reducing the Area of Pipelined Circuits",,"Proc. the 2006 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2006)",,,,"pp. 802-805",2006,Dec.
"高橋洋介,高橋篤司","クロックスケジューリングを用いた消費電力波形平滑化によるLSIのピーク電力削減手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2006-69)",,"Vol. 106","No. 388","pp. 27-32",2006,Nov.
"Yukihide Kohira,Atsushi Takahashi","A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2006-70)",,"Vol. 106","No. 388","pp. 33-38",2006,Nov.
"Yoichi Tomioka,Atsushi Takahashi","Routability Driven Via Assignment and Routing for 2-Layer Ball Grid Array Packages","Technical Committee on VLSI Design Technologies","IEICE Technical Report (VLD2006-76)",,"Vol. 106","No. 389","pp. 25-30",2006,Nov.
"高橋篤司","［招待講演］大域クロックを用いた一般同期回路 ?設計方法論，それらを支えるツール群，今後の展望?","システムLSI設計技術研究会","情報処理学会研究報告 (2006-SLDM-126)",,"Vol. 2006","No. 111","pp. 159-164",2006,Oct.
"高橋洋介,高橋篤司","クロックスケジューリングを用いたLSIのピーク電力削減手法","VLSI設計技術研究会","電子情報通信学会技術研究報告 (VLD2006-35)",,"Vol. 106","No. 254","pp. 7-12",2006,Sept.
"石田勉,小平行秀,高橋篤司","負閉路探索手法の性能評価","アルゴリズム研究会","情報処理学会研究報告 (2006-AL-107)",,"Vol. 2006","No. 71","pp. 45-50",2006,July
"富岡洋一,高橋篤司","BGAパッケージにおける配線混雑度を考慮した順行配線経路の自動生成手法",,"DAシンポジウム2006 論文集，情報処理学会シンポジウムシリーズ",,"Vol. 2006","No. 7","pp. 19-24",2006,July