"Jian Pang,Zheng Li,Ryo Kubozoe,Xueting Luo,Rui Wu,Yun Wang,Dongwon You,Ashbir Aviat Fadila,Rattanan Saengchan,Takeshi Nakamura,Joshua Alvin,Daiki Matsumoto,Bangan Liu,Aravind Tharayil Narayanan,Junjun Qiu,Hanli Liu,Zheng Sun,Hongye Huang,Korkut Kaan Tokgoz,K. Motoi,N. Oshima,S. Hori,K. Kunihiro,T. Kaneko,A. Shirane,K. Okada","A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR",,"IEEE Journal of Solid-State Circuits",,"Vol. 55","No. 9","pp. 2371-2386",2020,Sept.
"Hans Herdian,Haosheng Zhang,Aravind Tharayil Narayanan,Atsushi Shirane,Kenichi Okada","10GHz Varactor-less VCO with Helium-3 Ion Irradiated Inductor","IEEE Asia-Pacific Microwave Conference (APMC)",,,,,,2019,Dec.
"Haosheng Zhang,Herdian Hans,Tn Aravind,Atsushi Shirane,Mitsuru Suzuki,Kazuhiro Harasaka,Kazuhiko Adachi,Shigeyoshi Goka,Shinya Yanagimachi,Kenichi Okada","ULPAC: A Miniaturized Ultralow-Power Atomic Clock",,"IEEE Journal of Solid-State Circuits (JSSC)",,"Vol. 54","No. 11","pp. 3135-3148",2019,Nov.
"Haosheng Zhang,Aravind Tharayil Narayanan,Hans Herdian,Bangan Liu,Yun Wang,Atsushi Shirane,Kenichi Okada","0.2mW 70fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur","IEEE SSCS Japan Chapter VLSI Circuits報告会",,,,,,2019,July
"Aravind Tn,Kenichi Okada","A Pulse-Tail-Feedback LC-VCO with 700Hz Flicker Noise Corner and -195dBc FoM",,"IEICE Transactions on Electronics",,"Vol. E102-C","No. 7","pp. 595-606",2019,July
"Haosheng Zhang,Aravind Tharayil Narayanan,Hans Herdian,Bangan Liu,Yun Wang,Atsushi Shirane,Kenichi Okada","0.2mW 70fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur","IEEE Symposium on VLSI Circuits (VLSI Circuits)",,,,,,2019,June
"Yun Wang,Bangan Liu,Rui Wu,Hanli Liu,Tn Aravind,Jian Pang,Ning Li,Toru Yoshioka,Yuki Terashima,Haosheng Zhang,Dexian Tang,Makihiko Katsuragi,Daeyoung Lee,Sungtae Choi,Kenichi Okada,Akira Matsuzawa","A 60-GHz 3.0Gb/s Spectrum Efficient BPOOK Transceiver for Low-power Short-range Wireless in 65-nm CMOS",,"IEEE Journal of Solid-State Circuits (JSSC)",,"Vol. 54","No. 5","pp. 1363-1374",2019,May
"Jian Pang,Rui Wu,Yun Wang,Masato Dome,Hisashi Kato,Hongye Huang,Tn Aravind,Hanli Liu,Bangan Liu,Takeshi Nakamura,Takuya Fujimura,Masaru Kawabuchi,Ryo Kubozoe,Tsuyoshi Miura,Daiki Matsumoto,Zheng Li,Naoki Oshima,Keiichi Motoi,Shinichi Hori,Kazuaki Kunihiro,Tomoya Kaneko,Atsushi Shirane,Kenichi Okada","A 28GHz CMOS Phased-Array Transceiver Based on LO Phase Shifting Architecture with Gain Invariant Phase Tuning for 5G New Radio",,"IEEE Journal of Solid-State Circuits (JSSC)",,"Vol. 54","No. 5","pp. 1228-1242",2019,May
"Jian Pang,Shotaro Maki,Seitaro Kawai,Noriaki Nagashima,Yuuki Seo,Masato Dome,Hisashi Kato,Makihiko Katsuragi,Kento Kimura,Satoshi Kondo,Yuki Terashima,Hanli Liu,Teerachot Siriburanon,Tn Aravind,Nurul Fajri,Tohru Kaneko,Toru Yoshioka,Bangan Liu,Yun Wang,Rui Wu,Ning Li,Korkut Kaan Tokgoz,Masaya Miyahara,Atsushi Shirane,Kenichi Okada","A 50.1Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay with Calibration of LO Feed-Through and I/Q Imbalance",,"IEEE Journal of Solid-State Circuits (JSSC)",,"Vol. 54","No. 5","pp. 1375-1390",2019,May
"Zheng Li,Jian Pang,窪添 諒,Xueting Luo,Rui Wu,Yun Wang,Dongwon You,Ashbir Aviat Fadila,Rattanan Saengchan,中村 岳資,Joshua Alvin,松本 大輝,Aravind Tharayil Narayanan,Bangan Liu,白根 篤史,岡田 健一","A 28GHz CMOS Phased-Array Beamformer with Bi-Directional Technique for 5G NR","電子情報通信学会 LSIとシステムのワークショップ",,,,,,2019,May
"Haosheng Zhang,Hans Herdian,Aravind Tharayil Narayanan,白根 篤史,鈴木 暢,原坂 和宏,安達 一彦,柳町 真也,岡田 健一","An ultra-low-power atomic clock based on CMOS probing and locking loop","電子情報通信学会 LSIとシステムのワークショップ",,,,,,2019,May
"Haosheng Zhang,Tn Aravind,Hans Herdian,Bangan Liu,Rui Wu,Atsushi Shirane,Kenichi Okada","A Power-Efficient Pulse-VCO for Chip-Scale Atomic Clock",,"IEICE Transactions on Electronics",,"Vol. E102-C","No. 4","pp. 276-286",2019,Apr.
"Jian Pang,Zheng Li,窪添 諒,Xueting Luo,Rui Wu,Yun Wang,Dongwon You,Ashbir Aviat Fadila,Rattanan Saengchan,中村 岳資,Joshua Alvin,松本 大輝,THARAYILNAARAVIND,Bangan Liu,Junjun Qiu,Hanli Liu,Zheng Sun,Hongye Huang,白根 篤史,岡田 健一","双方向動作可能な5GNR二偏波MIMO対応28GHz帯CMOSフェーズドアレイ無線機","電子情報通信学会 集積回路研究会",,,"Vol. ICD2018-106","No. 507","pp. 31-35,",2019,Mar.
"Pang Jian,Zheng Li,Ryo Kubozoe,Xueting Luo,Rui Wu,Yun Wang,Dongwon You,Ashbir Aviat Fadila,Rattanan Saengchan,Takeshi Nakamura,Joshua Alvin,Daiki Matsumoto,Tn Aravind,Bangan Liu,Hanli Liu,Zheng Sun,Hongye Huang,Korkut Kaan Tokgoz,大島 直樹,元井 桂一,堀 真一,國弘 和明,Tomoya Kaneko,Atsushi Shirane,Kenichi Okada","A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR","IEEE SSCS Japan Chapter ISSCC報告会",,,,,,2019,Mar.
"Haosheng Zhang,Hans Herdian,Tn Aravind,Atsushi Shirane,Nobue Suzuki,原坂 和宏,安達 一彦,Shinya Yanagimach,Kenichi Okada","Ultra-Low-Power Atomic Clock for Satellite Constellation with 2.2x10-12 Long-Term Allan Deviation Using Cesium Coherent Population Trapping","IEEE SSCS Japan Chapter ISSCC報告会",,,,,,2019,Mar.
"Haosheng Zhang,Hans Herdian,Tn Aravind,Atsushi Shirane,Mitsuru Suzuki,Kazuhiro Harasaka,Kazuhiko Adachi,Shinya Yanagimachi,Kenichi Okada","Ultra-Low-Power Atomic Clock for Satellite Constellation with 2.2x10-12 Long-Term Allan Deviation Using Cesium Coherent Population Trapping","IEEE International Solid-State Circuits Conference (ISSCC)",,,,,"pp. 462-463",2019,Feb.
"Jian Pang,Zheng Li,Ryo Kubozoe,Xueting Luo,Rui Wu,Yun Wang,Dongwon You,Ashbir Aviat Fadila,Rattanan Saengchan,Takeshi Nakamura,Joshua Alvin,Daiki Matsumoto,Tn Aravind,Bangan Liu,Hanli Liu,Zheng Sun,Hongye Huang,Korkut Kaan Tokgoz,Naoki Oshima,Keiichi Motoi,Shinichi Hori,Kazuaki Kunihiro,Tomoya Kaneko,Atsushi Shirane,Kenichi Okada","A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR","IEEE International Solid-State Circuits Conference (ISSCC)",,,,,"pp. 344-345",2019,Feb.
"Bangan Liu,Huy Cu Ngo,Kengo Nakata,Wei Deng,Yuncheng Zhang,Junjun Qiu,Toru Yoshioka,Jun Emmei,Jian Pang,Tn Aravind,Haosheng Zhang,Dongsheng Yang,Hanli Liu,Teruki Someya,Atsushi Shirane,Kenichi Okada","A 0.4ps-Jitter -52dBc-Spur Synthesizable Injection-locked PLL with Self-clocked Non-overlap Update and Slope-balanced Sub-sampling BBPD",,"IEEE Solid-State Circuits Letters (SSC-L)",,"Vol. 2","No. 1","pp. 5-8",2019,Jan.
"Haosheng Zhang,Hans Herdian,Tn Aravind,Bangan Liu,Rui Wu,Atsushi Shirane,Kenichi Okada","A -194 dBc/Hz FoM VCO with Low-Supply Sensitivity for Ultra-Low-Power Atomic Clock","IEEE Asia-Pacific Microwave Conference (APMC)",,,,,,2018,Nov.
"Jian Pang,Rui Wu,Yun Wang,Masato Dome,Hisashi Kato,Hongye Huang,Tn Aravind,Hanli Liu,Wei Deng,Bangan Liu,Takeshi Nakamura,Takuya Fujimura,Masaru Kawabuchi,Ryo Kubozoe,Tsuyoshi Miura,Daiki Matsumoto,Naoki Oshima,Keiichi Motoi,Shinichi Hori,Kazuaki Kunihiro,Tomoya Kaneko,Kenichi Okada","A 28GHz CMOS Phased-Array Transceiver Using Gain-Invariant LO Phase Shifter with 0.1 Degree Beam-Steering Resolution for 5G New Radio","IEEE Radio Frequency Integrated Circuits Symposium (RFIC)",,,,,"pp. 56-59",2018,June
"Bangan Liu,Huy Cu Ngo,Kengo Nakata,Wei Deng,Yuncheng Zhang,Junjun Qiu,Toru Yoshioka,Jun Emmei,Haosheng Zhang,Jian Pang,Tn Aravind,Dongsheng Yang,Hanli Liu,Kenichi Okada,Akira Matsuzawa","A 1.2 ps-Jitter Fully-Synthesizable Fully-Calibrated Fractional-N Injection-Locked PLL Using True Arbitrary Nonlinearity Calibration Technique","IEEE Custom Integrated Circuits Conference (CICC)",,,,,,2018,Apr.
"Bangan Liu,Yun Wang,Jian Pang,Haosheng Zhang,Dongsheng Yang,Tn Aravind,Dae-Young Lee,SungTae Choi,Rui Wu,Kenichi Okada,Akira Matsuzawa","A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS",,"IEICE Transactions on Electronics",,"Vol. E101-C","No. 2","pp. 126-134",2018,Feb.
"Haosheng Zhang,Tn Aravind,Bangan Liu,Kenichi Okada,Akira Matsuzawa","A Pulse VCO With Tail-filter","IEEE Asia-Pacific Microwave Conference",,,,,,2017,Nov.
"Yun Wang,Bangan Liu,Hanli Liu,Tn Aravind,Jian Pang,Ning Li,Toru Yoshioka,Yuki Terashima,Haosheng Zhang,Dexian Tang,Makihiko Katsuragi,Daeyoung Lee,Sungtae Choi,Rui Wu,Kenichi Okada,Akira Matsuzawa","A 100mW 3.0Gb/s Spectrum Efficient 60GHz Bi-Phase OOK CMOS Transceiver","IEEE Symposium on VLSI Circuits",,,,,,2017,June
"Tn Aravind,Ning Li,Kenichi Okada,Akira Matsuzawa","A Pulse-Tail-Feedback VCO Achieving FoM of 195dBc/Hz with Flicker Noise Corner of 700Hz","IEEE Symposium on VLSI Circuits (VLSI Circuits)",,,,,,2017,June
"Tn Aravind,Ning Li,岡田 健一,松澤 昭","A Pulse-Tail-Feedback VCO Achieving FoM of 195dBc/Hz with Flicker Noise Corner of 700Hz","IEEE SSCS Japan Chapter VLSI Circuits報告会",,,,,,2017,June
"ARAVIND THARAYIL NARAYANAN","CMOS集積回路による分周器を用いない低ジッタクロック発生器の研究",,,,,,,2017,Mar.
"ARAVIND THARAYIL NARAYANAN","A Study of Low-Jitter Divider-Less CMOS Clock Generators",,,,,,,2017,Mar.
"ARAVIND THARAYIL NARAYANAN","A Study of Low-Jitter Divider-Less CMOS Clock Generators",,,,,,,2017,Mar.
"Tn Aravind,Wei Deng,Dongsheng Yang,Rui Wu,Kenichi Okada,Akira Matsuzawa","A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI",,"IEICE Transactions on Electronics",,"Vol. E100-C","No. 3","pp. 259-267",2017,Mar.
"ARAVIND THARAYIL NARAYANAN","A Study of Low-Jitter Divider-Less CMOS Clock Generators",,,,,,,2017,Mar.
"Dongsheng Yang,Wei Deng,Bangan Liu,Tn Aravind,Teerachot Siriburanon,Kenichi Okada,Akira Matsuzawa","An HDL-Synthesized Injection-Locked PLL Using LC-Based DCO for On-chip Clock Generation","IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC),",,,,,,2017,Jan.
"Hanli Liu,Ning Li,Tn Aravind,Teerachot Siriburanon,Takeshi Inoue,Hitoshi Sakane,Takuichi Hirano,Kenichi Okada,Akira Matsuz","A -194.0dBc/Hz FoM CMOS Tail-Filtering VCO Using Helium-3 Ion Irradiation Technique","IEEE MTT-S European Microwave Conference",,,,,,2016,Oct.
"Haosheng Zhang,Tn Aravind,Kenichi Okada,Akira Matsuzawa","An Analysis of Pulse-VCO with Tail-Filter","電子情報通信学会 ソサイエティ大会",,,,,"  C-12-6",2016,Sept.
"Dongsheng Yang,Wei Deng,Yuki Terashima,Teerachot Siriburanon,Tn Aravind,Toru Yoshioka,Kenichi Okada,Akira Matsuzawa","An LC-VCO based Synthesizable Injection-Locked PLL with an FoM of -250.3dB","IEEE European Solid-State Circuits Conference (ESSCIRC)",,,,,,2016,Sept.
"Tn Aravind,Makihiko Katsuragi,Kento Kimura,Satoshi Kondo,Korkut Kaan Tokgoz,Kengo Nakata,Wei Deng,Kenichi Okada,Akira Matsuzawa","A Fractional-N Sub-Sampling PLL Using a Pipelined Phase-Interpolator with an FoM of -250dB",,"IEEE Journal of Solid-State Circuits","IEEE","Vol. 51","No. 7","pp. 1630-1640",2016,July
"Dongsheng Yang,Tomohiro Ueno,Wei Deng,Kengo Nakata,Tn Aravind,Rui Wu,Kenichi Okada,Akira Matsuzawa","A 0.0055mm2 480?W Synthesizable PLL using Stochastic TDC in 28nm FDSOI",,"IEICE Transactions on Electronics","IEICE","Vol. E99-C","No. 6","pp. 632-640",2016,June
"Tharayil Narayanan Aravind,Makihiko Katsuragi,Kengo Nakata,Yuki Terashima,Kenichi Okada,Akira Matsuzawa","A Noise Reduction Technique for Divider-Less Fractional-N Frequency Synthesizer using Phase-Interpolation Technique","IEEE ACM Asia South Pacific Design Automation Conference",,,,,,2016,Jan.
"Dongsheng Yang,Wei Deng,Tharayil Narayanan Aravind,Kengo Nakata,Teerachot Siriburanon,Kenichi Okada,Akira Matsuzawa","An Automatic Place-and-Routed Two-Stage Fractional-N Injection-locked PLL Using Soft Injection","IEEE ACM Asia South Pacific Design Automation Conference",,,,,,2016,Jan.
"Kento Kimura,Tn Aravind,Kenichi Okada,Akira Matsuzawa","An AM-PM Noise Mitigation Technique in Class-C VCO",,"IEICE Transactions on Electronics, 2015","IEICE","Vol. E98-C","No. 12","pp. 1161-1170",2015,Dec.
"Tn Aravind,Kenichi Okada,Akira Matsuzawa","A Fractional-N Sub-Sampling PLL with -246dB FoM","STARCフォーラム",,,,,,2015,Nov.
"Aravind Tharayil Narayanan,Makihiko Katsuragi,Kento Kimura,Satoshi Kondo,Korkut Kaan Tokgoz,Yuki Terashima,Wei Deng,Kenichi Okada,Akira Matsuzawa","A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with an FoM of -246dBc/Hz","IEEE European Solid-State Circuits Conference (ESSCIRC)",,,,,,2015,Sept.
"Tn Aravind,Makihiko Katsuragi,Kento Kimura,Kenichi Okada,Akira Matsuzawa","A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator aided DTC","電子情報通信学会 ソサイエティ大会",,,,,,2015,Sept.
"桂木 真希彦,THARAYILNAARAVIND,岡田 健一,松澤 昭","位相補間回路の高精度化に関する検討","電子情報通信学会 ソサイエティ大会",,,,,,2015,Sept.
"ファムヴァン トゥアン,近藤 智史,THARAYILNAARAVIND,岡田 健一,松澤 昭","Class-C 型CMOS VCOにおける最適バイアス制御回路の検討","電子情報通信学会 ソサイエティ大会",,,,,,2015,Sept.
"Dongsheng Yang,Wei Deng,Tn Aravind,Rui Wu,Bangan Liu,Kenichi Okada,Akira Matsuzawa","A Fully Synthesizable Injection-Locked PLL with Feedback Current Output DAC in 28nm FDSOI",,"IEICE Electronics Express","IEICE","Vol. 12","No. 15","pp. 1-11",2015,Aug.
"中田 憲吾,Wei Deng,Dongsheng Yang,上野 智大,THARAYILNAARAVIND,Teerachot Siriburanon,近藤 智史,岡田 健一,松澤 昭","注入同期を利用した自動合成配置配線可能なAll Digital Synthesizable PLL","電子情報通信学会 LSIとシステムのワークショップ",,,,,,2015,May
"Ning Li,Kenichi Okada,Takeshi Inoue,Takuichi Hirano,Qinghong Bu,Tn Aravind,Teerachot Siriburanon,Hitoshi Sakane,Akira Matsuzawa","High-Q Inductors on Locally Semi-Insulated Si Substrate by Helium-3 Bombardment for RF CMOS Integrated Circuits",,"IEEE Transactions on Electron Devices","IEEE","Vol. 62","No. 4","pp. 1269-1275",2015,Apr.
".Wei Deng,Dongsheng Yang,Aravind Tharayil Narayanan,,Kengo Nakata,Teerachot Siriburanon,Kenichi Okada,Akira Matsuzawa","A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique","IEEE SSCS Kansai Chapter ISSCC報告会",,,,,,2015,Mar.
"Wei Deng,Dongsheng Yang,Tn Aravind,Kengo Nakata,Teerachot Siriburanon,Kenichi Okada,Akira Matsuzawa","A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique","IEEE International Solid-State Circuits Conference (ISSCC),",,,,,,2015,Feb.
"Tn Aravind,Wei Deng,Kenichi Okada,Akira Matsuzawa","A Tail-Current Modulated VCO with Adaptive-Bias Scheme","EEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC)",,,,,,2015,Jan.
"Tn Aravind,Kento Kimura,Wei Deng,Kenichi Okada,Akira Matsuzawa","A Pulse-Driven VCO with Enhanced Efficiency","電子情報通信学会 アナログRF研究会",,,"Vol. RF2014-2",,"p. 2",2014,Dec.
"Aravind Tharayil Narayanan,Wei Deng,Kenichi Okada,Akira Matsuzawa","A Tail-Current Modulated VCO with Adaptive Start-up Scheme","Vietnam Japan MicroWave",,,,,,2014,Nov.
"AravindTharayil Narayanan,Wei Deng,Yang Dongsheng,Wu Rui,Kenichi Okada,Akira Matsuzawa","A 0.011 mm2 PVT‐Robust Fully‐Synthesizable CDR with a Data Rate of 10.05 Gb/S Using Injection‐","IEEE Asian Solid-State Circuits Conference (A-SSCC)",,,,,,2014,Nov.
"Aravind Tharayil Narayanan,Wei Deng,Kenichi Okada,Akira Matsuzawa","A Tail-Current Modulated VCO with Adaptive Startup Scheme","Thailand-Japan Microwave (TJMW2014)",,,,,,2014,Nov.
"Aravind Tharayil Narayanan,Wei Deng,Kenichi Okada,Akira Matsuzawa","A Tail-Feedback VCO with Self-Adjusting Current Modulation Scheme","IEEE MTT-S European Microwave Conference (EuMC)",,,,,,2014,Oct.
"Aravind Tharayil Narayanan,Kento Kimura,Wei Deng,Kenichi Okada,Akira Matsuzawa","A Pulse-Driven LC-VCO with a Figure-of-Merit of -192dBc/Hz,","IEEE European Solid-State Circuits Conference (ESSCIRC)",,,,,,2014,Sept.
"ning li,Kenichi Okada,Takeshi Inoue,Takuichi Hirano,Qinghong Bu,Aravind Tharayil Narayanan,Teerachot Siriburanon,Hotoshi Sakane,Akira Matsuzawa","High-Q Inductors on Locally Semi-Insulated Si Substrate by Helium-3 Bombardment for RF CMOS Integrated Circuits","応用物理学会 シリコンテクノロジー分科会",,,,,,2014,Aug.
"Ning Li,Kenichi Okada,Takeshi Inoue,Takuichi Hirano,Qinghong Bu,Aravind Tharayil Narayanan,Teerachot Siriburanon,Hitoshi Sakane,Akira Matsuzawa","High-Q Inductors on Locally Semi-Insulated Si Substrate by Helium-3 Bombardment for RF CMOS Integrated Circuits","IEEE Symposium on VLSI Technology (VLSI Technology)",,,,,"pp. 189-190",2014,June