"Tamon Sadasue","C/C++ Based System Level RTL Design Methodology and Its Design Efficiency Using LLVM Compiler Infrastructure",,,,,,,2023,Mar.
"Tamon Sadasue","C/C++ Based System Level RTL Design Methodology and Its Design Efficiency Using LLVM Compiler Infrastructure",,,,,,,2023,Mar.
"Tamon Sadasue","C/C++ Based System Level RTL Design Methodology and Its Design Efficiency Using LLVM Compiler Infrastructure",,,,,,,2023,Mar.
"Tamon Sadasue,Tsuyoshi Isshiki","LLVM-C2RTL: C/C++ Based System Level RTL Design Framework Using LLVM Compiler Infrastructure",,"IPSJ Transactions on System and LSI Design Methodology",,"Vol. 16",,"pp. 12 - 26",2023,Feb.
"Tamon Sadasue,Takuya Tanaka,Ryosuke Kasahara,Arief Darmawan,Tsuyoshi Isshiki","Scalable Hardware Architecture for fast Gradient Boosted Tree Training",,"IPSJ Transactions on System LSI Design Methodology",,"Vol. 14",,"pp. 11 - 20",2021,Feb.
"Tamon Sadasue,Tsuyoshi Isshiki","Scalable Full Hardware Logic Architecture for Gradient Boosted Tree Training","IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)",,,,,,2020,May