@article{CTT100547370,
  author = {Bakhtiar Affendi Rosdi and Atsushi Takahashi},
  title = {Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements},
  journal = {IEICE Trans. Fundamentals},
  year = 2007,
}

@article{CTT100525842,
  author = {Bakhtiar Affendi Rosdi and Atsushi Takahashi},
  title = {Multi-clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits},
  journal = {IEICE Trans. Fundamentals},
  year = 2006,
}

@inproceedings{CTT100547376,
  author = {Bakhtiar Affendi Rosdi and Atsushi Takahashi},
  title = {Delay Balancing by Min-Cut Algorithm for Reducing the Area of Pipelined Circuits},
  booktitle = {Proc. the 20th Workshop on Circuits and Systems in Karuizawa},
  year = 2007,
}

@inproceedings{CTT100525851,
  author = {Bakhtiar Affendi Rosdi and Atsushi Takahashi},
  title = {Replacement of Register with Delay Element for Reducing the Area of Pipelined Circuits},
  booktitle = {Proc. the 2006 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2006)},
  year = 2006,
}

@inproceedings{CTT100525859,
  author = {Bakhtiar Affendi Rosdi and Atsushi Takahashi},
  title = {Low Area Pipelined Circuits by Multi-clock Cycle Path and Clock Scheduling},
  booktitle = {Proc. Asia and South Pacific Design Automation Conference 2006 (ASP-DAC 2006)},
  year = 2006,
}

@inproceedings{CTT100540974,
  author = {Bakhtiar Affendi Rosdi and Atsushi Takahashi},
  title = {An Algorithm to Calculate the Minimum Clock Period of a Semi-synchronous Circuit that Contains Multi-clock Cycle Path},
  booktitle = {IEICE Technical Report (VLD2005-8)},
  year = 2005,
}

@inproceedings{CTT100539579,
  author = {Bakhtiar Affendi Rosdi and Atsushi Takahashi},
  title = {Reduction on the Usage of Intermediate Registers for Pipelined Circuits},
  booktitle = {Proc. the 12th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2004)},
  year = 2004,
}