論文

• Bakhtiar Affendi Rosdi, Atsushi Takahashi. Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements, IEICE Trans. Fundamentals, Vol. E90-A, No. 12, pp. 2736-2742, Dec. 2007.
• Bakhtiar Affendi Rosdi, Atsushi Takahashi. Multi-clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits, IEICE Trans. Fundamentals, Vol. E89-A, No. 12, pp. 3435-3442, Dec. 2006.  公式リンク  
  

国際会議発表 (査読有り)

• Bakhtiar Affendi Rosdi, Atsushi Takahashi. Replacement of Register with Delay Element for Reducing the Area of Pipelined Circuits, Proc. the 2006 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2006), pp. 802-805, Dec. 2006.
• Bakhtiar Affendi Rosdi, Atsushi Takahashi. Low Area Pipelined Circuits by Multi-clock Cycle Path and Clock Scheduling, Proc. Asia and South Pacific Design Automation Conference 2006 (ASP-DAC 2006), pp. 260-265, Jan. 2006.
• Bakhtiar Affendi Rosdi, Atsushi Takahashi. Reduction on the Usage of Intermediate Registers for Pipelined Circuits, Proc. the 12th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2004), pp. 333-338, Oct. 2004.

国内会議発表 (査読有り)

• Bakhtiar Affendi Rosdi, Atsushi Takahashi. Delay Balancing by Min-Cut Algorithm for Reducing the Area of Pipelined Circuits, Proc. the 20th Workshop on Circuits and Systems in Karuizawa, pp. 643-648, Apr. 2007.

国内会議発表 (査読なし・不明)

• Bakhtiar Affendi Rosdi, Atsushi Takahashi. An Algorithm to Calculate the Minimum Clock Period of a Semi-synchronous Circuit that Contains Multi-clock Cycle Path, Technical Committee on VLSI Design Technologies, IEICE Technical Report (VLD2005-8), Vol. 105, No. 58, pp. 13-18, May 2005.

[ BibTeX 形式で保存 ]    [ 論文・著書をCSV形式で保存 ]    [ 特許をCSV形式で保存 ]