論文

• Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector, IEICE Transactions on Electronics, Vol. E102-C, No. 7, pp. 520-529, July 2019.
• Mitsutoshi Sugawara, Kenji Mori, Zule Xu, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E9-A, No. 12, pp. 2435-2443, Dec. 2017.
• Zule Xu, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. A 3.6GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC, IEEE Journal of Solid-State Circuits, IEEE, Vol. 51, No. 10, pp. 2345-2356, Oct. 2016.
• Zule Xu, Seung Jong Lee, Masaya Miyahara, Akira Matsuzawa. Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E98-A, No. 2, pp. 476-484, Feb. 2015.
• Zule Xu, Masaya Miyahara, Akira Matsuzawa. Picosecond Resolution Time-to-Digital Converter Using Gm-C Integrator and SAR-ADC, IEEE Transactions on Nuclear Science, Vol. 61, No. 2, pp. 852-859, Apr. 2014.

国際会議発表 (査読有り)

• Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. A 2GHz 3.1mW Type-I Digital Ring-Based PLL, IEEE European Solid-State Circuits Conference (ESSCIRC),, Sept. 2016.
• Anugerah Firdauzi, Zule Xu, Masaya Nohara (Miyahara), Akira Matsuzawa. A 74.5 dB SNDR 1 MHz Bandwidth 1.17 mW Delta-Sigma Time to Digital Converter Using Charge-Pump and SAR ADC, IEEE International Symposium on Circuits ans Systems 2016, May 2016.
• James Lin, Zule Xu, Masaya Miyahara, Akira Matsuzawa. A 0.5-to-1 V 9-Bit 15-to-90 Ms/S Digitally Interpolated Pipelined-SAR ADC Using Dynamic Amplifier, IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2014.
• Zule Xu, Mitsutoshi Sugawara, Kenji Mori, Masaya Miyahara, Akira Matsuzawa. A Varactor-Less and Dither-Less LC-Digitally Controlled Oscillator with 9-bit Fine Bank, 0.26 mm2 Area, and 6.7 kHz Frequency Resolution, International Conference on Solid State Devices and Materials (SSDM), Sept. 2014.
• Zule Xu, Mitsutoshi Sugawara, Masaya Miyahara, Akira Matsuzawa. A 0.8 ps-LSB, 10-bit, 0.018 mm2 Time-to-Digital Converter, International Conference on Solid State Devices and Materials (SSDM), Sept. 2014.
• Zule Xu, Seung Jong Lee, Masaya Miyahara, Akira Matsuzawa. A 0.84ps-LSB 2.47mW Time-to-Digital Converter Using Charge Pump and SAR-ADC, IEEE Custom Integrated Circuits Conference (CICC), Sept. 2013.
• Zule Xu, Masaya Miyahara, Akira Matsuzawa. A 1ps-Resolution Integrator-Based Time-to-Digital Converter Using a SAR-ADC in 90nm CMOS, IEEE International New Circuits and Systems Conference (NEWCAS), June 2003.

国内会議発表 (査読なし・不明)

• 徐 祖楽, 木村 悟利, 岡田 健一, 宮原 正也. CTGS圧電単結晶振動子を用いた世界最小電力基準クロック発生回路, 電子情報通信学会 LSIとシステムのワークショップ, May 2021.
• Anugerah Firdauzi, Zule Xu, Masaya Nohara (Miyahara), Akira Matsuzawa. A Low-Power Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Charge-Pump and SAR ADC, IEICE Technical Committee on Integrated Circuit and Devices (ICD), Aug. 2016.
• Anugerah Firdauzi, Xu Zule, Masaya Miyahara, Akira Matsuzawa. Delta-Sigma Time to Digital Converter Using Charge Pump and SAR ADC, 電子情報通信学会 総合大会, Mar. 2015.
• Zule Xu, Seung Jong Lee, Masaya Miyahara, Akira Matsuzawa. A 0.84ps-LSB 2.47mW Time-to-Digital Converter Using Charge Pump and SAR-ADC, 電子情報通信学会 アナログRF研究会, Nov. 2013.
• 徐祖楽, 宮原正也, 松澤昭. 積分器とSARADCを用いた1ps分解能の時間・デジタル変換器, LSIとシステムのワークショップ, May 2013.

学位論文

• Charge-Domain Time-to-Digital Converter and Its Application to Fractional-N Frequency Synthesizer,  Exam Summary,  博士（学術）,  Tokyo Institute of Technology,  2015/03/26,   
• Charge-Domain Time-to-Digital Converter and Its Application to Fractional-N Frequency Synthesizer,  Summary,  博士（学術）,  Tokyo Institute of Technology,  2015/03/26,   
• Charge-Domain Time-to-Digital Converter and Its Application to Fractional-N Frequency Synthesizer,  Thesis,  Doctor (Academic),  Tokyo Institute of Technology,  2015/03/26, 
• Charge-Domain Time-to-Digital Converter and Its Application to Fractional-N Frequency Synthesizer,  Outline,  博士（学術）,  Tokyo Institute of Technology,  2015/03/26,   

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