論文

• Kazutoshi Hirose, Jaehoon Yu, Kota Ando, Yasuyuki Okoshi, Angel Lopez Garcia-Arias, Junnosuke Suzuki, Thiem Van Chu, Kazushi Kawamura, Masato Motomura. Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet, International Solid-State Circuits Conference, Feb. 2022.
• Junnosuke Suzuki, Tomohiro Kaneko, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu. ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation, International Journal of Networking and Computing, July 2021.
• Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Jaehoon Yu, Masato Motomura. Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture, IEEE Access, Vol. 9, pp. 6179-6187, Jan. 2021.
• Kodai Ueyoshi, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura. Dither NN: hardware/algorithm co-design for accurate quantized neural networks, IEICE Transactions on Information and Systems, Vol. E102-D, No. 12, Dec. 2019.
• Ueyoshi K., Ando K., Hirose K, Takamaeda-Yamazaki S., Hamada M., Kurorda T., Motomura M.. QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3D SRAM Using Inductive Coupling Technology in 40-nm CMOS, IEEE Journal of Solid-State Circuits, Vol. 54, No. 1, Jan. 2019.

国際会議発表 (査読有り)

• Yasuyuki Okoshi, Angel Lopez Garcia-Arias, Kazutoshi Hirose, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu. Multicoated Supermasks Enhance Hidden Networks, International Conference on Machine Learning, July 2022.
• Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura. Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner, Hot Chips, Aug. 2021.
• Junnosuke Suzuki, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu. ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation, International Symposium on Computing and Networking (CANDAR), Nov. 2020.

国内会議発表 (査読なし・不明)

• 平山 侑樹, 廣瀬 一俊, 安藤 洸太, 植吉 晃大, 浅井 哲也, 本村 真人, 高前田 伸也. ベイジアンNNのHW実装に向けたサンプリング手法の検討, 電子情報通信学会研究会報告CPSY2019-35, July 2019.
• 廣瀬 一俊, 浅井 哲也, 本村 真人, 高前田 伸也. エッジ環境におけるニューラルネットワーク学習軽量化手法の検討, 電子情報通信学会研究会報告CPSY2019-7, June 2019.
• 池田 泰我, 植吉 晃大, 安藤 洸太, 廣瀬 一俊, 浅井 哲也, 本村 真人, 高前田 伸也. 効率的なDNN計算のための無効ニューロン予測手法の評価, 情報処理学会システム・アーキテクチャ研究会, June 2019.
• 植吉 晃大, 池田 泰我, 安藤 洸太, 廣瀬 一俊, 浅井 哲也, 高前田 伸也, 本村 真人. 無効ニューロン予測によるDNN計算効率化手法, 電子情報通信学会研究会報告RECONF2019-18, May 2019.
• 7. 安藤 洸太, 植吉 晃大, 大羽 由華, 工藤 巧, 池辺 将之, 浅井 哲也, 高前田 伸也, 安藤 洸太, 植吉 晃大, 大羽 由華, 廣瀬 一俊, 工藤 巧, 池辺 将之, 浅井 哲也, 高前田 伸也, 本村 真人. Dither NN: 画像処理から着想を得た組込み向け量子化ニューラルネットワークの精度向上手法, 電子情報通信学会研究会報告RECONF2019-14, May 2019.

学位論文

• A Study of Redundancy-Aware Neural Network Model Constructions: From Training Techniques to Architectural Realization,  Summary,  Doctor (Engineering),  Tokyo Institute of Technology,  2022/03/26, 
• A Study of Redundancy-Aware Neural Network Model Constructions: From Training Techniques to Architectural Realization,  Exam Summary,  Doctor (Engineering),  Tokyo Institute of Technology,  2022/03/26, 
• A Study of Redundancy-Aware Neural Network Model Constructions: From Training Techniques to Architectural Realization,  Thesis,  Doctor (Engineering),  Tokyo Institute of Technology,  2022/03/26, 

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