国際会議発表 (査読有り)

• Dingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang, Zheng Sun, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada. A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2024.

国内会議発表 (査読なし・不明)

• Waleed Madany, Hongye Huang, Bangan Liu, 白根 篤史, 岡田 健一. A Fully Synthesizable DPLL for Spread Spectrum Clock Generation, 電子情報通信学会 総合大会, Mar. 2024.

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