国際会議発表 (査読有り)

• Dingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang, Zheng Sun, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada. A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2024.
• Waleed Madany, Yuncheng Zhang, Ashbir Aviat Fadila, Hongye Huang, Junjun Qiu, Atsushi Shirane, Kenichi Okada. A Fully Synthesizable DPLL with Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation Path, IEEE European Solid-State Circuits Conference (ESSCIRC), Sept. 2023.
• Dingxin Xu, Yuncheng Zhang, Hongye Huang, Zheng Sun, Bangan Liu, Ashbir Aviat Fadila, Junjun Qiu, Zezheng Liu, Wenqian Wang, Yuang Xiong, Waleed Madany, Atsushi Shirane, Kenichi Okada. A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference, IEEE Custom Integrated Circuits Conference (CICC), Apr. 2023.
• Junjun Qiu, Wenqian Wang, Zheng Sun, Bangan Liu, Yuncheng Zhang, Dingxin Xu, Hongye Huang, Ashbir Aviat Fadila, Zezheng Liu, Waleed Madany, Yuang Xiong, Atsushi Shirane, Kenichi Okada. A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain Boosted PD and Loop Gain Calibration, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023.

国内会議発表 (査読なし・不明)

• Waleed Madany, Hongye Huang, Bangan Liu, 白根 篤史, 岡田 健一. A Fully Synthesizable DPLL for Spread Spectrum Clock Generation, 電子情報通信学会 総合大会, Mar. 2024.
• Yuncheng Zhang, Zheng Sun, Bangan Liu, Junjun Qiu, Dingxin Xu, Yi Zhang, Xi Fu, Dongwon You, Hongye Huang, Waleed Madany, Ashbir Aviat Fadila, Zezheng Liu, Wenqian Wang, Yuang Xiong, Atsushi Shirane, Kenichi Okada. A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit DSM and Transformer Combined FIR, IEEE SSCS Japan Chapter VLSI Circuits報告会, July 2023.

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